參數(shù)資料
型號(hào)： AD6636BC
廠商： Analog Devices, Inc.
元件分類： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁數(shù)： 61/72頁
文件大小： 1629K
代理商： AD6636BC
AD6636
<2>: Port CD Amplitude Correction Enable Bit. When this bit is
set, the amplitude correction function of the I/Q correction
logic for the AB port is enabled. When this bit is cleared, the
amplitude correction value is given by the value of the AB
amplitude correction register. If the Port A complex data active
bit of the ADC input control register is cleared (real input
mode), this bit is a don’t care.
Rev. 0 | Page 61 of 72
<1>: Port CD Phase Correction Enable Bit. When this bit is set,
the phase correction function of the I/Q correction logic for the
AB port is enabled. When this bit is cleared, the phase
correction value is given by the value of the AB phase
correction register. If the Port A complex data active bit of the
ADC input control register is cleared (real input mode), this bit
is a don’t care.
<0>: Port CD DC Correction Enable Bit. When the dc
correction enable bit is set, the dc offset correction function of
the I/Q correction block for the AB port is enabled. When
cleared, the dc offset correction value is given by the value of
the AB offset correction registers. If the Port A complex data
active bit of the ADC input control register is cleared (real input
mode), this bit is a don’t care.
Port AB, DC Offset Correction I <15:0>
This register holds the in-phase signal dc offset correction value
for complex data stream when dc correction is enabled. This
value should be set manually when automatic correction is
disabled. This 16-bit value is subtracted from the 16-bit ADC
Port A data (in-phase signal). This data is a don’t care in real
input mode.
Port AB, DC Offset Correction Q <15:0>
This register holds the quadrature phase signal dc offset
correction value for complex data stream when dc correction
enabled. This value should be set manually when automatic
correction is disabled. This 16-bit value is subtracted from the
16-bit ADC Port B data (quadrature phase signal). This data is a
don’t care in real input mode.
Port CD, DC Offset Correction I <15:0>
This register holds the in-phase signal dc offset correction value
for complex data stream when dc correction is enabled. This
value should be set manually when automatic correction is
disabled. This 16-bit value is subtracted from the 16-bit ADC
Port C data (in-phase signal). This data is a don’t care in real
input mode.
Port CD, DC Offset Correction Q <15:0>
This register holds the quadrature phase signal dc offset
correction value for complex data stream when dc correction is
enabled. This value should be set manually when automatic
correction is disabled. This 16-bit value is subtracted from the
16-bit ADC Port D data (quadrature phase signal). This data is a
don’t care in real input mode.
Port AB, Phase Offset Correction <15:0>
This register holds the phase offset correction value for complex
data stream when the AB port phase correction is enabled. This
value is set manually when automatic correction is disabled.
This value is calculated as tan(phase_mismatch), where
phase_mismatch is the mismatch in phase between I (in-phase
signal) and Q (quadrature phase signal). This 14-bit value is
multiplied with 16-bit Q (quadrature phase signal, Input Port B)
and added to 16-bit I (in-phase signal, Input Port A). This data
is a don’t care in real input mode.
Port AB, Amplitude Offset Correction <15:0>
complex data stream when the AB port amplitude correction is
enabled. This value is set manually when automatic correction
is disabled. This value is calculated as (Mag(Q) Mag(I)),
where I is the in-phase signal and Q is the quadrature phase
signal. This 14-bit value is multiplied with 16-bit Q (quadrature
phase signal, Input Port B) and added to 16-bit Q (quadrature
phase signal, Input Port B). This data is a don’t care in real input
mode.
Port CD, Phase Offset Correction <15:0>
This register holds the phase offset correction value for the
complex data stream when CD port phase correction is enabled.
This value should be set manually when automatic correction is
disabled. This value should be calculated as tangent
(phase_mismatch), where phase_mismatch is the mismatch in
phase between I (in-phase signal) and Q (quadrature phase
signal). This 14-bit value is multiplied with 16-bit Q
(quadrature phase signal, Input Port D) and added to 16-bit I
(in-phase signal, Input Port C). This data is a don’t care in real
input mode.
Port CD, Amplitude Offset Correction <15:0>
This register holds the amplitude offset correction value for
complex data stream when CD port amplitude correction is
enabled. This value is set manually when automatic correction
is disabled. This value is calculated as (Mag(Q) Mag(I)),
where I is the in-phase signal and Q is the quadrature phase
signal. This 14-bit value are multiplied with 16-bit Q
(quadrature phase signal, Input Port D) and added to 16-bit Q
(quadrature phase signal, Input Port D). This data is a don’t care
in real input mode.
Port A Gain Control <7:0>
<7>: This bit is open.
<6:1>: This 6-bit word specifies the relinearization pipe delay to
be used in the ADC input gain control block. The decimal
representation of these bits is the number of input clock cycle
pipeline delays between the external EXP data output and the
internal application of relinearization based on EXP.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6636BC/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk
AD6636BC/PCBZ 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk
AD6636CBC 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD6636CBCZ 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3）
AD6636CBCZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC)
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