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參數(shù)資料
| 型號(hào)： | AD6636BC |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 44/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636BC |
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AD6636
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal. In Figure 40, PxACK is already
pulled high and, therefore, the 16-bit I data is output on the data
bus on the next PCLK rising edge after PxREQ is driven logic
high. The PxIQ signal also goes high to indicate that I data is
available on the data bus. The next PCLK cycle brings the
Q data onto the data bus. In this cycle, the PxIQ signal is driven
low. When I data and Q data are output, the channel indicator
pins PxCH[2:0] indicate the data source (AGC number).
Rev. 0 | Page 44 of 72
Figure 40 is the timing diagram for interleaved I/Q mode with
the AGC gain word disabled. Figure 41 is a similar timing
diagram with the AGC gain word. I and Q data are as explained
for Figure 40. In the PCLK cycle after the Q data, the AGC gain
word is output on the data bus and the PxGAIN signal is pulled
high to indicate that the gain word is available on the parallel
port. Therefore, a minimum of three or four PCLK cycles are
required to output one sample of output data on the parallel
port without or with the AGC gain word, respectively.
Parallel IQ Mode
In this mode, eight bits of I data and eight bits of Q data are
output on the data bus simultaneously during one PCLK cycle.
The I byte is the most significant byte of the port, while the Q
byte is the least significant byte. The PAIQ and PBIQ output
indicator pins are set high during the PCLK cycle. Note that if
data from multiple AGCs are output consecutively, the PAIQ
and PBIQ output indicator pins remain high until data from all
channels is output.
The PACH[2:0] and PBCH[2:0] pins provide a 3-bit binary
value indicating the source (AGC number) of the data currently
being output. Figure 42 is the timing diagram for parallel I/Q
mode.
PCLKn
t
DPREQ
PxREQ
PxACK
DPP
Px [15:0]
I[15:0]
Q[15:0]
PxIQ
t
DPIQ
PxCH [2:0]
PxCH [2:0] = CHANNEL #
t
DPCH
GAIN [11:0] +
0000
PxGAIN
t
DPGAIN
0
Figure 41. Interleaved I/Q Mode with an AGC Gain Word
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636BC/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636CBC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD6636CBCZ | 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
| AD6636CBCZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
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