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參數(shù)資料
| 型號： | AD6636BC |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 60/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636BC |
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AD6636
<7>: Channel 1 Complex Data Input Bit. Similar to Bit <23> for
Channel 1.
Rev. 0 | Page 60 of 72
<6:4>: Channel 1 Crossbar Mux Select Bits. Similar to Bits
<22:20> for Channel 1.
<3>: Channel 0 Complex Data Input Bit. Similar to Bit <23> for
Channel 0.
<2:0>: Channel 0 Crossbar Mux Select Bits. Similar to Bits
<22:20> for Channel 0.
ADC CLK Control Register <11:0>
These bits control the ADC clocks and internal PLL clock.
<11>: ADC Port D CLK Invert Bit. When this bit is set, the
inverted ADC Port D clock is used to register ADC input port
D data into the part. When this bit is cleared, the clock is used as
is, without any inversion or phase change.
<10>: ADC Port C CLK Invert Bit. Similar to Bit <11> for ADC
Port C.
<9>: ADC Port B CLK Invert Bit. Similar to Bit <11> for ADC
Port B.
<8>: ADC Port A CLK Invert Bit. Similar to Bit <11> for ADC
Port A.
<7:6>: ADC Pre PLL Clock Divider Bits. These bits control the
PLL clock divider. The PLL clock is derived from the ADC
Port A clock.
Table 32. PLL Clock Divider Select Bits
PLL Clock Divider Bits <12:11>
00
01
10
11
Divide-by Value
Divide-by-1, bypass
Divide-by-2
Divide-by-4
Divide-by-8
<5:1>: PLL Clock Multiplier Bits. These bits control the PLL
clock multiplier. The output of the PLL clock divider is
multiplied with the binary value of these bits. The valid range
for the multiplier is from 4 to 20. A value outside this range
powers down the PLL, and the PLL clock is the same as the
ADC Port A clock.
<0>: This bit is open (write Logic 0).
Port AB, I/Q Correction Control <15:0>
<15:12>: Amplitude Loop BW. These bits set the decimation
value used in the integrator for the amplitude offset-estimation
feedback loop. A value of 0 sets a decimation of 2
12
and a value
of 11 sets decimation of 2
24
. Each increment of these bits
increases the decimation value by a power of 2.
<11:8>: Phase Loop BW. These bits set the decimation value
used in the integrator for the phase offset-estimation feedback
loop. A value of 0 sets a decimation of 2
12
and a value of 11 sets
decimation of 2
24
. Each increment of these bits increases the
decimation value by a power of 2.
<7:4>: DC Loop BW. These bits set the decimation and
interpolation value used in the low-pass filters for the dc offset
estimation feedback loop. A value of 0 sets a decimation/
interpolation of 2
12
and a value of 11 sets decimation/
interpolation of 2
24
. Each increment of these bits increases the
decimation/interpolation value by a power of 2.
<3>: Reserved.
<2>: Port AB Amplitude Correction Enable Bit. When the
amplitude correction enable bit is set, the amplitude correction
function of the I/Q correction logic for the AB port is enabled.
When this bit cleared, the amplitude correction value is given by
the value of the AB amplitude correction register. If the Port A
complex data active bit of the ADC input control register is
cleared (real input mode), this bit is a don’t care.
<1>: Port AB Phase Correction Enable Bit. When this bit is set,
the phase correction function of the I/Q correction logic for the
AB port is enabled. When this bit is cleared, the phase correc-
tion value is given by the value of the AB phase correction
register. If the Port A complex data active bit of the ADC input
control register is cleared (real input mode), this bit is a don’t
care.
<0>: Port AB DC Correction Enable Bit. When this bit is set, the
dc offset correction function of the I/Q correction block for the
AB port is enabled. When this bit is cleared, the dc offset
correction value is given by the value of the AB offset correction
registers. If the Port A complex data active bit of the ADC input
control register is cleared (real input mode), this bit is a don’t
care.
Port CD, I/Q Correction Control <15:0>
<15:12>: Amplitude Loop BW. These bits set the decimation
value used in the integrator for the amplitude offset estimation
feedback loop. A value of 0 sets a decimation of 2
12
and a value
of 11 sets decimation of 2
24
. Each increment of these bits
increases the decimation value by a power of 2.
<11:8>: Phase Loop BW. These bits set the decimation value
used in the integrator for the phase offset estimation feedback
loop. A value of 0 sets a decimation of 2
12
and a value of 11 sets
decimation of 2
24
. Each increment of these bits increases the
decimation value by a power of 2.
<7:4>: DC Loop BW. These bits set the decimation and
interpolation value used in the low pass filters for the dc offset
estimation feedback loop. A value of 0 sets a decimation/
interpolation of 2
12
and a value of 11 sets decimation/
interpolation of 2
24
. Each increment of these bits increases the
decimation/interpolation value by a power of 2.
<3>: Reserved.
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| AD6636CBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636BC/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636CBC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD6636CBCZ | 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
| AD6636CBCZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
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