參數(shù)資料
型號(hào)： AD6636BC
廠商： Analog Devices, Inc.
元件分類： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁(yè)數(shù)： 6/72頁(yè)
文件大?。?/td> 1629K
代理商： AD6636BC
AD6636
GENERAL TIMING CHARACTERISTICS
Rev. 0 | Page 6 of 72
Table 3. General Timing Characteristics
1, 2
Parameter
CLK TIMING REQUIREMENTS
t
CLK
CLKx Period (x = A, B, C, D)
t
CLKL
CLKx Width Low (x = A, B, C, D)
t
CLKH
CLKx Width High (x = A, B, C, D)
t
CLKSKEW
CLKA to CLKx Skew (x = B, C, D)
INPUT WIDEBAND DATA TIMING REQUIREMENTS
t
SI
INx [15:0] to
↑
CLKx Setup Time (x = A, B, C, D)
t
HI
INx [15:0] to
↑
CLKx Hold Time (x = A, B, C, D)
t
SEXP
EXPx [2:0] to
↑
CLKx Setup Time (x = A, B, C, D)
t
HEXP
EXPx [2:0] to
↑
CLKx Hold Time (x = A, B, C, D)
t
DEXP
↑
CLKx to EXPx[2:0] Delay (x = A, B, C, D)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER)
t
DPREQ
↑
PCLK to
↑
Px REQ Delay (x = A, B, C)
t
DPP
↑
PCLK to Px [15:0] Delay (x = A, B, C)
t
DPIQ
↑
PCLK to Px IQ Delay (x = A, B, C)
t
DPCH
↑
PCLK to Px CH[2:0] Delay (x = A, B, C)
t
DPGAIN
↑
PCLK to Px Gain Delay (x = A, B, C)
t
SPA
Px ACK to
↑
PCLK Setup Time (x = A, B, C)
t
HPA
Px ACK to
↑
PCLK Hold Time (x = A, B, C)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE)
t
PCLK
PCLK Period
t
PCLKL
PCLK Low Period
t
PCLKH
PCLK High Period
t
DPREQ
↑
PCLK to
↑
Px REQ Delay (x = A, B, C)
t
DPP
↑
PCLK to Px [15:0] Delay (x = A, B, C)
t
DPIQ
↑
PCLK to Px IQ Delay (x = A, B, C)
t
DPCH
↑
PCLK to Px CH[2:0] Delay (x = A, B, C)
t
DPGAIN
↑
PCLK to Px Gain Delay (x = A, B, C)
t
SPA
Px ACK to
↓
PCLK Setup Time (x = A, B, C)
t
HPA
Px ACK to
↓
PCLK Hold Time (x = A, B, C)
MISC PINS TIMING REQUIREMENTS
t
RESET
RESET Width Low
t
DIRP
CPUCLK/SCLK to IRP Delay
t
SS
SYNC(0, 1, 2, 3) to
↑
CLKA Setup Time
t
HS
SYNC(0, 1, 2, 3) to
↑
CLKA Hold Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
I
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
Min
6.66
1.71
1.70
t
CLK
1.3
0.75
1.13
3.37
1.11
5.98
1.77
2.07
0.48
0.38
0.23
4.59
0.90
5.0
1.7
0.7
4.72
4.8
4.83
4.88
5.08
6.09
1.0
30
0.87
0.67
Typ
0.5 × t
CLK
0.5 × t
CLK
0.5 × t
PCLK
0.5 × t
PCLK
7.5
Max
10.74
3.86
5.29
5.49
5.35
4.95
8.87
8.48
10.94
10.09
11.49
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
2
C
LOAD
= 40 pF on all outputs, unless otherwise noted.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6636BC/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk
AD6636BC/PCBZ 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk
AD6636CBC 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD6636CBCZ 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3）
AD6636CBCZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC)
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