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| 型號(hào)： | AD9276-80KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL HI SPEED FPGA AD9276 |
| 設(shè)計(jì)資源： | AD9276/77 Eval Brd Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 733 mVpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 195mW @ 40MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9276 |
| 已供物品： | 板 |
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AD9276
Rev. 0 | Page 31 of 48
0.6
0.5
0.4
0.3
0.2
0.1
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
GAIN+ (V)
IN
P
U
T
FU
L
S
C
A
L
E
(
V
p-
p)
08
18
0-
0
51
PGA GAIN = 21dB
PGA GAIN = 24dB
PGA GAIN = 27dB
PGA GAIN = 30dB
Figure 57. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
IN
P
U
T
FU
L
S
C
A
L
E
(
V
p-
p)
GAIN+ (V)
PGA GAIN = 21dB
PGA GAIN = 30dB
08
18
0
-05
2
PGA GAIN = 27dB
PGA GAIN = 24dB
Figure 58. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations
Variable Gain Amplifier (VGA)
The differential X-AMP VGA provides precise input attenu-
ation and interpolation. It has a low input-referred noise of
3.8 nV/√Hz and excellent gain linearity. A simplified block
diagram is shown in Figure 59.
VIP
GAIN±
3.5dB
VIN
gm
POSTAMP
+
–
GAIN INTERPOLATOR
08
18
0-
05
3
Figure 59. Simplified VGA Schematic
The input of the VGA is a 14-stage differential resistor ladder with
3.5 dB per tap. The resulting total gain range is 42 dB, which
allows for range loss at the endpoints. The effective input resistance
per side is 180 Ω nominally for a total differential resistance of
360 Ω. The ladder is driven by a fully differential input signal from
the LNA. LNA outputs are dc-coupled to avoid external decoupling
capacitors. The common-mode voltage of the attenuator and the
VGA is controlled by an amplifier that uses the same midsupply
voltage derived in the LNA, permitting dc coupling of the LNA
to the VGA without introducing large offsets due to common-
mode differences. However, any offset from the LNA becomes
amplified as the gain increases, producing an exponentially
increasing VGA output offset.
The input stages of the X-AMP are distributed along the ladder,
and a biasing interpolator, controlled by the gain interface, deter-
mines the input tap point. With overlapping bias currents, signals
from successive taps merge to provide a smooth attenuation range
from 42 dB to 0 dB. This circuit technique results in linear-in-dB
gain law conformance and low distortion levels—only deviating
±0.5 dB or less from the ideal. The gain slope is monotonic with
respect to the control voltage and is stable with variations in
process, temperature, and supply.
The X-AMP inputs are part of a programmable gain feedback
amplifier that completes the VGA. Its bandwidth is approximately
100 MHz. The input stage is designed to reduce feedthrough to
the output and to ensure excellent frequency response uniformity
across the gain setting.
Gain Control
The gain control interface, GAIN±, is a differential input. VGAIN
varies the gain of all VGAs through the interpolator by selecting
the appropriate input stages connected to the input attenuator.
For GAIN at 0.8 V, the nominal GAIN+ range for 28.5 dB/V is
0 V to 1.6 V, with the best gain linearity from about 0.16 V to
1.44 V, where the error is typically less than ±0.5 dB. For GAIN+
voltages greater than 1.44 V and less than 0.16 V, the error
increases. The value of GAIN+ can exceed the supply voltage
by 1 V without gain foldover.
Gain control response time is less than 750 ns to settle within 10%
of the final value for a change from minimum to maximum gain.
The GAIN+ and GAIN pins can be interfaced in one of two
ways. Using a single-ended method, a Kelvin type of connec-
tion to ground can be used, as shown in Figure 60. For driving
multiple devices, it is preferable to use a differential method, as
shown in Figure 61. In either method, the GAIN+ and GAIN
pins should be dc-coupled and driven to accommodate a 1.6 V
full-scale input.
GAIN+
GAIN–
100
0V TO 1.6V DC
50
0.01F
KELVIN
CONNECTION
081
80
-05
4
Figure 60. Single-Ended GAIN+, GAIN Pin Configuration
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