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| 型號： | AD9276-80KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL HI SPEED FPGA AD9276 |
| 設(shè)計資源： | AD9276/77 Eval Brd Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 733 mVpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 195mW @ 40MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9276 |
| 已供物品： | 板 |
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AD9276
Rev. 0 | Page 34 of 48
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated as follows:
SNR Degradation = 20 × log10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 68).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9276.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the original
clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
NR
(
d
B
)
08
18
0-
06
2
0.25ps
Figure 68. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
the AD9276 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and the bias current of the
LVDS output drivers.
400
0
SAMPLING FREQUENCY (MSPS)
CURR
E
NT
(
m
A)
350
300
250
200
150
100
50
10
30
20
40
50
60
70
80
08
18
0-
0
63
IAVDD1, 80MSPS SPEED GRADE
IAVDD1, 65MSPS SPEED GRADE
IAVDD1, 40MSPS SPEED GRADE
IDRVDD
Figure 69. Supply Current vs. fSAMPLE for fIN = 5 MHz
220
170
0
SAMPLING FREQUENCY (MSPS)
P
O
W
E
R
/C
HANNE
L
(
m
W
)
10
30
20
50
40
60
80
70
215
210
205
200
195
190
185
180
175
08
18
0-
0
64
80MSPS SPEED GRADE
65MSPS SPEED GRADE
40MSPS SPEED GRADE
Figure 70. Power per Channel vs. fSAMPLE for fIN = 5 MHz
The AD9276 features scalable LNA bias currents (see Table 18,
Register 0x12). The default LNA bias current settings are high.
Figure 71 shows the typical reduction of AVDD2 current with
each bias setting. It is also recommended that the LNA offset be
adjusted using Register 0x10 (see Table 18) when the LNA bias
setting is low.
0
50
100
150
200
250
300
350
400
HIGH
L
NA
BI
AS
S
E
T
IN
G
MID-HIGH
MID-LOW
LOW
TOTAL AVDD2 CURRENT (mA)
08
180
-06
5
Figure 71. AVDD2 Current at Different LNA Bias Settings, fSAMPLE = 40 MSPS
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