參數(shù)資料
型號： AD9276-80KITZ
廠商： Analog Devices Inc
文件頁數(shù)： 38/48頁
文件大小： 0K
描述： BOARD EVAL HI SPEED FPGA AD9276
設(shè)計(jì)資源： AD9276/77 Eval Brd Gerber Files
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 733 mVpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 195mW @ 40MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9276
已供物品： 板
AD9276
Rev. 0 | Page 43 of 48
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Comments
0x0F
flex_channel_input
Filter cutoff frequency control
0000 = 1.3 × 1/3 × fSAMPLE
0001 = 1.2 × 1/3 × fSAMPLE
0010 = 1.1 × 1/3 × fSAMPLE
0011 = 1.0 × 1/3 × fSAMPLE (default)
0100 = 0.9 × 1/3 × fSAMPLE
0101 = 0.8 × 1/3 × fSAMPLE
0110 = 0.7 × 1/3 × fSAMPLE
1000 = 1.3 × 1/4.5 × fSAMPLE
1001 = 1.2 × 1/4.5 × fSAMPLE
1010 = 1.1 × 1/4.5 × fSAMPLE
1011 = 1.0 × 1/4.5 × fSAMPLE
1100 = 0.9 × 1/4.5 × fSAMPLE
1101 = 0.8 × 1/4.5 × fSAMPLE
1110 = 0.7 × 1/4.5 × fSAMPLE
X
0x30
Antialiasing filter
cutoff (global).
0x10
flex_offset
X
6-bit LNA offset adjustment
10 0000 for LNA bias high, mid-high, mid-low (default)
10 0001 for LNA bias low
0x20
LNA force offset
correction
(local).
0x11
flex_gain
X
PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
11 = 30 dB
LNA gain
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
0x06
LNA and PGA gain
adjustment
(global).
0x12
bias_current
X
1
X
LNA bias
00 = high (default)
01 = mid-high
10 = mid-low
11 = low
0x08
LNA bias current
adjustment
(global).
0x14
output_mode
X
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
1596.3
similar)
X
Output
invert
enable
1 = on
0 = off
(default)
Data format select
00 = offset binary
(default)
01 = twos
complement
0x00
Configures the
outputs and the
format of the data
(Bits[7:3] and
Bits[1:0] are global;
Bit 2 is local).
0x15
output_adjust
X
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
DCO±
and
FCO±
2× drive
strength
1 = on
0 = off
(default)
0x00
Determines LVDS
or other output
properties.
Primarily functions
to set the LVDS
span and
common-mode
levels in place of
an external resistor
(Bits[7:1] are global;
Bit 0 is local).
0x16
output_phase
X
0011 = output clock phase adjust
(0000 through 1010)
(Default: 180° relative to data edge)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge
0100 = 240° relative to data edge
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = 420° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03
On devices that
utilize global
clock divide,
determines which
phase of the
divider output is
used to supply
the output clock.
Internal latching
is unaffected.
0x18
flex_vref
X
0 =
internal
reference
1 =
external
reference
X
0x00
Select internal
reference
(recommended
default) or
external reference
(global).
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