參數(shù)資料
型號(hào)： AD9276-80KITZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 40/48頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL HI SPEED FPGA AD9276
設(shè)計(jì)資源： AD9276/77 Eval Brd Gerber Files
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 733 mVpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 195mW @ 40MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9276
已供物品： 板
AD9276
Rev. 0 | Page 45 of 48
APPLICATIONS INFORMATION
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9276, it is recommended that
two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one 1.8 V supply is
available, it should be routed to the AVDD1 pin first and then
tapped off and isolated with a ferrite bead or a filter choke
preceded by decoupling capacitors for the DRVDD pin. The
user should employ several decoupling capacitors on all
supplies to cover both high and low frequencies. Locate these
capacitors close to the point of entry at the PCB level and close
to the part, with minimal trace lengths.
A single PCB ground plane should be sufficient when using the
AD9276. With proper decoupling and smart partitioning of the
analog, digital, and clock sections of the PCB, optimum perfor-
mance can be easily achieved.
EXPOSED PADDLE THERMAL HEAT SLUG
RECOMMENDATIONS
It is required that the exposed paddle on the underside of the
device be connected to analog ground to achieve the best elec-
trical and thermal performance of the AD9276. An exposed
continuous copper plane on the PCB should mate to the AD9276
exposed paddle, Pin 0. The copper plane should have several vias
to achieve the lowest possible resistive thermal path for heat
dissipation to flow through the bottom of the PCB. These vias
should be solder-filled or plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the device and
the PCB, partition the continuous copper plane into several uni-
form sections by overlaying a silkscreen or solder mask on the
PCB. This ensures several tie points between the AD9276 and
the PCB during the reflow process, whereas using one continuous
plane with no partitions guarantees only one tie point. See
Figure 78 for a PCB layout example. For detailed information
about packaging and for more PCB layout examples, see the
AN-772 Application Note, A Design and Manufacturing Guide
for the Lead Frame Chip Scale Package (LFCSP), at
SILKSCREEN PARTITION
PIN 1 INDICATOR
08
18
0-
07
0
Figure 78. Typical PCB Layout
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