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參數(shù)資料
| 型號： | AD9517-2A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 76/80頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9517-2A |
| 設(shè)計資源： | AD9517 Eval Brd Schematics AD9517 Gerber Files AD9517-2 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9517-2A |
| 主要屬性： | 2 輸入，12 輸出，2.2GHz VCO |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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AD9517-2
Data Sheet
Rev. E | Page 78 of 80
CMOS CLOCK DISTRIBUTION
The AD9517 provides four clock outputs (OUT4 to OUT7)
that are selectable as either CMOS or LVDS level outputs.
When selected as CMOS, each output becomes a pair of CMOS
outputs, each of which can be individually turned on or off and
set as noninverting or inverting. These outputs are 3.3 V CMOS
compatible.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be used.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net.
Series termination at the source is generally required to provide
transmission line matching and/or to reduce current transients
at the driver. The value of the resistor is dependent on the board
design and timing requirements (typically 10 to 100 is used).
CMOS outputs are also limited in terms of the capacitive load
or trace length that they can drive. Typically, trace lengths of less
than 3 inches are recommended to preserve signal rise/fall times
and preserve signal integrity.
CMOS
10
60.4
(1.0 INCH)
MICROSTRIP
06426-
076
Figure 75. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9517 do not supply enough current
to provide a full voltage swing with a low impedance resistive,
far-end termination, as shown in Figure 76. The far-end
termination network should match the PCB trace impedance and
provide the desired switching point. The reduced signal swing
may still meet receiver input requirements in some applications.
This can be useful when driving long trace lengths on less
critical nets.
CMOS
10
50
100
VS
06426-
077
Figure 76. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9517 offers both LVPECL and
LVDS outputs that are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
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