參數(shù)資料
型號(hào): AD9522-5BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 10/76頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 2.4GHZ 64LFCSP
標(biāo)準(zhǔn)包裝: 750
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:12,2:24
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
AD9522-5
Rev. 0 | Page 18 of 76
Pin No.
Input/
Output
Pin
Type
Mnemonic
Description
47
O
LVDS or
CMOS
OUT3 (OUT3B)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
48
O
LVDS or
CMOS
OUT3 (OUT3A)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
50
O
LVDS or
CMOS
OUT2 (OUT2B)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
51
O
LVDS or
CMOS
OUT2 (OUT2A)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
52
O
LVDS or
CMOS
OUT1 (OUT1B)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
53
O
LVDS or
CMOS
OUT1 (OUT1A)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
55
O
LVDS or
CMOS
OUT0 (OUT0B)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
56
O
LVDS or
CMOS
OUT0 (OUT0A)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
58
O
Current set
resistor
RSET
Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin
to GND.
62
O
Current set
resistor
CPRSET
Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND.
This resistor can be omitted if the PLL is not used.
63
I
Reference
input
REFIN (REF2)
Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF2.
64
I
Reference
input
REFIN (REF1)
Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF1.
EPAD
GND
The exposed die pad must be connected to GND.
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