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參數(shù)資料
型號(hào)： AD9522-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 26/76頁
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.4GHZ 64LFCSP
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9522-5
Rev. 0 | Page 32 of 76
Table 25. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
fREF (MHz)
R
P
A
B
N
fVCO (MHz)
Mode
Notes
10
1
X1
1
10
FD
P = 1, B = 1 (bypassed)
10
1
2
X1
1
2
20
FD
P = 2, B = 1 (bypassed)
10
1
X1
3
30
FD
P = 1, B = 3
10
1
X1
4
40
FD
P = 1, B = 4
10
1
X1
5
50
FD
P = 1, B = 5
10
1
2
X1
3
6
60
FD
P = 2, B = 3
10
1
2
0
3
6
60
DM
P and P + 1 = 2 and 3, A = 0, B = 3
10
1
2
1
3
7
70
DM
P and P + 1 = 2 and 3, A = 1, B = 3
10
1
2
3
8
80
DM
P and P + 1 = 2 and 3, A = 2, B = 3
10
1
2
1
4
9
90
DM
P and P + 1 = 2 and 3, A = 1, B = 4
10
1
2
X1
5
10
100
FD
P = 2, B = 5
10
1
2
0
5
10
100
DM
P and P + 1 = 2 and 3, A = 0, B = 5
10
1
2
1
5
11
110
DM
P and P + 1 = 2 and 3, A = 1, B = 5
10
1
2
X1
6
12
120
FD
P = 2, B = 6
10
1
2
0
6
12
120
DM
P and P + 1 = 2 and 3, A = 0, B = 6
10
1
4
0
3
12
120
DM
P and P + 1 = 4 and 5, A = 0, B = 3
10
1
4
1
3
13
130
DM
P and P + 1 = 4 and 5, A = 1, B = 3
1 X = don’t care.
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the
DLD function is available at the LD, STATUS, and REFMON pins.
The digital lock detect circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
The lock detect window timing depends on the value of the
CPRSET resistor, as well as three settings: the digital lock
detect window bit (0x018[4]), the antibacklash pulse width
bit (0x017[1:0], see Table 2), and the lock detect counter
(0x018[6:5]). The lock and unlock detection values in Table 2
are for the nominal value of CPRSET = 5.1 kΩ. Doubling the
CPRSET value to 10 kΩ doubles the values in Table 2.
A lock is not indicated until there is a programmable number of
consecutive PFD cycles with a time difference less than the lock
detect threshold. The lock detect circuit continues to indicate a
lock until a time difference greater than the unlock threshold
occurs on a single subsequent cycle. For the lock detect to work
properly, the period of the PFD frequency must be greater than
the unlock threshold. The number of consecutive PFD cycles
required for lock is programmable (0x018[6:5]).
Note that it is possible in certain low (<500 Hz) loop bandwidth,
high phase margin cases that the DLD can chatter during acqui-
sition, which can cause the AD9522 to automatically enter and exit
holdover. To avoid this problem, it is recommended that the
user make provisions for a capacitor to ground on the LD pin so
that current source digital lock detect (CSDLD) mode can be used.
Analog Lock Detect (ALD)
The AD9522 provides an ALD function that can be selected for
use at the LD pin. There are two operating modes for ALD.
N-channel open-drain lock detect. This signal requires a
pull-up resistor to the positive supply, VS. The output is
normally high with short, low going pulses. Lock is
indicated by the minimum duty cycle of the low going pulses.
P-channel open-drain lock detect. This signal requires a
pull-down resistor to GND. The output is normally low with
short, high going pulses. Lock is indicated by the minimum
duty cycle of the high going pulses.
The analog lock detect function requires an RC filter to provide a
logic level indicating lock/unlock. The ADIsimCLK tool can be
used to help the user select the right passive component values
for ALD to ensure its correct operation.
AD9522
ALD
LD
R1
C
VOUT
R2
VS = 3.3V
072
40
-06
7
Figure 31. Example of Analog Lock Detect Filter Using
N-Channel Open-Drain Driver
Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is possible by using the
current source digital lock detect function.
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