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參數(shù)資料
| 型號： | AD9522-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 71/76頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.4GHZ 64LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9522-5
Rev. 0 | Page 73 of 76
APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9522
The AD9522 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9522, the following guidelines
should be kept in mind.
The AD9522 has four frequency dividers: the reference (or R)
divider, the feedback (or N) divider, the VCO divider, and the
channel divider. When trying to achieve a particularly difficult
frequency divide ratio requiring a large amount of frequency
division, some of the frequency division can be done by either
the VCO divider or the channel divider, thus allowing a higher
phase detector frequency and more flexibility in choosing the
loop bandwidth.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current, and thus allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. ADIsimCLK is a very accurate
tool for determining the optimal loop filter for a given application.
USING THE AD9522 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock of the AD9522. An ADC can be thought of as a
sampling mixer, and any noise, distortion, or time jitter on the
clock is combined with the desired signal at the analog-to-
digital output. Clock integrity requirements scale with the analog
input frequency and resolution, with higher analog input
frequency applications at ≥14-bit resolution being the most
stringent. The theoretical SNR of an ADC is limited by the ADC
resolution and the jitter on the sampling clock. Considering an
ideal ADC of infinite resolution where the step size and
quantization error can be ignored, the available SNR can be
expressed approximately by
π
=
J
At
f
SNR
2
1
20log
(dB)
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 57 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
fA (MHz)
S
NR
(
d
B)
EN
O
B
10
1k
100
30
40
50
60
70
80
90
100
110
6
8
10
12
14
16
18
t
J
= 100f
s
t
J
= 200f
s
t
J
= 400f
s
t
J
= 1ps
t
J
= 2ps
t
J
= 10p
s
SNR = 20log
1
2πfAtJ
07
24
0-
04
4
Figure 57. SNR and ENOB vs. Analog Input Frequency
See the AN-756 Application Note and the AN-501 Application
Note at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sampling clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.
The differential LVDS outputs of the AD9522 enable clock
solutions that maximize converter SNR performance.
The input requirements of the ADC (differential or single-
ended, logic level termination) should be considered when
selecting the best clocking/converter solution. In some cases,
the LVPECL outputs of the AD9522 may be desirable for
clocking a converter instead of the LVDS outputs of the AD9522.
LVDS CLOCK DISTRIBUTION
The AD9522 provides clock outputs that are selectable as either
CMOS or LVDS level outputs. LVDS is a differential output
option that uses a current mode output stage. The nominal
current is 3.5 mA, which yields 350 mV output swing across a
100 Ω resistor. An output current of 7 mA is also available in
cases where a larger output swing is required. The LVDS output
meets or exceeds all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 58. If ac coupling is necessary, place decoupling
capacitors either before or after the 100 Ω termination resistor.
VS
LVDS
VS
LVDS
100
DIFFERENTIAL (COUPLES)
07
240
-04
7
Figure 58. LVDS Output Termination
See the AN-586 Application Note at www.analog.com for more
information on LVDS.
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