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參數(shù)資料
| 型號： | AD9522-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/76頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.4GHZ 64LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9522-5
Rev. 0 | Page 29 of 76
Phase-Locked Loop (PLL)
PROGRAMMABLE
N DELAY
CLK
R
DI
V
IDE
R
CL
O
CK
DO
UBL
E
R
STATUS
PR
O
G
R
A
MM
A
B
L
E
R
DE
L
AY
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
RE
NCE
HOLD
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
ZERO DELAY BLOCK
FROM CHANNEL
DIVIDER 0
07
24
0-
0
64
REFIN
REF1
REF2
BUF
AMP
REFERENCE
SWITCHOVER
REF_SEL
REFIN
STATUS
OPTIONAL
Figure 28. PLL Functional Block Diagram
The AD9522 includes on-chip PLL blocks that can be used with
an external VCO or VCXO to create a complete phase-locked
loop. The PLL requires an external loop filter, which usually
consists of a small number of capacitors and resistors. The
configuration and components of the loop filter help to
establish the loop bandwidth and stability of the PLL.
The AD9522 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be used to
clean up jitter and phase noise on a noisy reference. The exact
choice of PLL parameters and loop dynamics is application specific.
The flexibility and depth of the AD9522 PLL allow the part to
be tailored to function in many different applications and signal
environments.
Configuration of the PLL
Configuration of the PLL is accomplished by programming
the various settings for the R divider, N divider, PFD polarity,
and charge pump current. The combination of these settings
determines the PLL loop bandwidth. These are managed through
by the design of the external loop filter.
Successful PLL operation and satisfactory PLL loop performance
are highly dependent on proper configuration of the PLL
settings, and the design of the external loop filter is crucial to
the proper operation of the PLL.
ADIsimCLK is a free program that can help with the design
and exploration of the capabilities and features of the AD9522,
including the design of the PLL loop filter. The AD9516 model
found in ADIsimCLK Version 1.2 can also be used for modeling
the AD9522 loop filter. It is available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R divider and the N divider and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD
transfer function and minimizes phase noise and reference
spurs. The antibacklash pulse width is set by 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD. The maximum input frequency into the
PFD is a function of the antibacklash pulse setting, as specified
in the phase/frequency detector (PFD) parameter in Table 2.
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs and
tells the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the external VCO to move the VCO frequency
up or down. The CP can be set (0x010[3:2]) for high impedance
(allows holdover operation), for normal operation (attempts to
lock the PLL loop), for pump-up, or for pump-down (test modes).
The CP current is programmable in eight steps from (nominally)
0.6 mA to 4.8 mA. The exact value of the CP current LSB is set
by the CPRSET resistor, which is nominally 5.1 kΩ.
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