參數(shù)資料
型號(hào)： AD9547/PCBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 23/104頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9547
設(shè)計(jì)資源： AD9547 Schematic
AD9574 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9547
主要屬性： 2 個(gè)差分式或 4 個(gè)單端輸入
次要屬性： CMOS，LVPECL 和 LVDS 兼容
已供物品： 板
Data Sheet
AD9547
Rev. E | Page 25 of 104
The clock distribution parameters reside in the 0x0400 register
address space. They include the following:
Output power-down control
Output enable (disabled by default)
Output synchronization
Output mode control
Output divider functionality
Program the reference inputs.
10. The reference input parameters reside in the 0x0500
register address space. They include the following:
Reference power-down
Reference logic family
Reference profile assignment control
Phase build-out control
11. Program the reference profiles.
The reference profile parameters reside in the 0x0600 and
0x0700 register address spaces. They include the following:
Reference priority
Reference period
Reference period tolerance
Reference validation timer
Reference redetect timer
Digital loop filter coefficients
Reference prescaler (R divider)
Feedback dividers (S, U, and V)
Phase and frequency lock detector controls
12. Generate reference acquisition.
After the registers are programmed, issue an I/O update using
Register 0x0005, Bit 0 to invoke all of the register settings that have
been programmed up to this point.
If the settings are programmed for manual profile assignment,
the DPLL locks to the first available reference that has the highest
priority. If the settings are programmed for automatic profile
assignment, then write to the reference profile selection register
(Address 0x0A0D) to select the state machines that require starting.
Next, issue an I/Oupdate (Address 0x0005, Bit 0) tostart the
selected state machines. Upon completion of the reference
detection sequence, the DPLL locks to the first available
reference with the highest priority.
13. Generate the output clock.
If the registers are programmed for automatic clock distribution
synchronization via DPLL phase or frequency lock, the synthesized
output signalappears at the clock distribution outputs (assuming
that the output is enabled and the DDS output signal has been
routed to the CLKINx input pins). Otherwise, set and then clear
the sync distribution bit (Address 0x0A02, Bit 1) or use a multi-
function pin input (if programmed accordingly) to generate
a clock distribution sync pulse, which causes the synthesized
output signal to appear at the clock distribution outputs.
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