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參數(shù)資料
| 型號： | AD9547/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/104頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9547 |
| 設(shè)計資源： | AD9547 Schematic AD9574 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9547 |
| 主要屬性： | 2 個差分式或 4 個單端輸入 |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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Data Sheet
AD9547
Rev. E | Page 51 of 104
SPI Mode Operation
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB-first
and LSB-first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9547 uses the bidirectional MSB-first mode. The bidirectional
mode is the default mode so that the user can still write to the
device to switch to unidirectional mode, if it is wired for
unidirectional operation.
Assertion (active low) of the CS pin initiates a write or read
operation to the AD9547 SPI port. For data transfers of three
bytes or fewer (excluding the instruction word), the device
supports the CS stalled high mode (see Table 31). In this mode,
the CS pin can be temporarily deasserted on any byte boundary,
allowing time for the system controller to process the next
byte. CS can be deasserted only on byte boundaries, however.
This applies to both the instruction and data portions of the
transfer.
Table 31. Byte Transfer Count
W1
W0
Bytes to Transfer
0
1
0
1
2
1
0
3
1
Streaming mode
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, the state machine must be
reset either by completing the transfer or by asserting the CS
pin for at least one complete SCLK cycle (but less than eight
SCLK cycles). Deasserting the CS pin on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 31), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented. CS must be deas-
serted at the end of the last byte transferred, thereby ending the
stream mode.
CommunicationCycle—InstructionPlus Data
The SPI protocol consists of a two-part communication cycle.
The first part is a 16-bit instruction word that is coincident with
the first 16 SCLK rising edges and a payload. The instruction word
provides the AD9547 serialcontrol port with information regard-
ing the payload. The instruction word includes the R/W bit that
indicates the direction of the payload transfer (that is, a read or
write operation). The instruction word also indicates the number
of bytes in the payload and the starting register address of the
first payload byte.
Write
If the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9547. Data
bits are registered on the rising edge of SCLK. The length of the
transfer (1, 2, or 3 bytes or streaming mode) depends on the W0
and W1 bits (see Table 31) in the instruction byte. When not
streaming, CS can be deasserted after each sequence of eight
bits to stall the bus (except after the last byte, where it ends the
cycle). When the bus is stalled, the serial transfer resumes
when CS is asserted. Deasserting the CS pin on a nonbyte
boundary resets the serial control port. Reserved or blank
registers are not skipped over automatically during a write
sequence. Therefore, the user must know what bit pattern to
write to the reserved registers to preserve proper operation of
the part. Generally, it does not matter what data is written toblank
registers, but it is customaryto write 0s.
Most of the serial port registers are buffered. Refer to the
Buffered/Active Registers section for details on the difference
between buffered and active registers. Therefore, data written
into buffered registers does not immediately take effect. An addi-
tional operation is needed totransfer buffered serial controlport
contents to the registers that actually control the device. This is
accomplished with an I/O update operation that is performed in
one of two ways: by writing a Logic 1 toRegister 0x0005, Bit 0 (this
bit is self-clearing) or by using an external signalvia an
appropriately programmed multifunction pin. The user can
change as many register bits as desired before executing an I/O
update. The I/O update operation transfers the buffer register
contents to their active register counterparts.
Read
The AD9547 supports the long instruction mode only. If the
instruction word indicates a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in the
instruction word. N is the number of data bytes read and depends
on the W0 and W1 bits of the instruction word.
During a SPI read, serial data on SDIO (or SDO in the case of
4-wire mode) transitions on the SCLK falling edge, and is
normally sampled on the SCLK rising edge. To read the last bit
correctly, the SPI host must be able to tolerate a zero hold time. If
zero hold time is not possible, the user can either use streaming
mode and delaythe rising edge of CS, or sample the serial data on
the SCLK falling edge. However, to correctly sample the data on
the SCLK falling edge, the user must ensure that the setup time
is greater than tDV(time data valid). Blank registers are not
skipped over during readback.
A readback operation takes data from either the serial control
port buffer registers or the active registers, as determined by
Register 0x0004, Bit 0.
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