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| 型號(hào)： | AD9547/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 98/104頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9547 |
| 設(shè)計(jì)資源： | AD9547 Schematic AD9574 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9547 |
| 主要屬性： | 2 個(gè)差分式或 4 個(gè)單端輸入 |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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Data Sheet
AD9547
Rev. E | Page 93 of 104
STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D19)
All bits in Register 0x0D00 to Register 0x0D19 are read only. These registers are accessible during EEPROM transactions. Register 0x0D00 and
Register 0x0D01 require an IO_UPDATE (Register 0x0005 = 0x01) in order to reflect their latest status.
Table 134. EEPROM Status
Address
Bit
Bit Name
Description
0x0D00
[7:3]
Unused
Unused.
2
Fault detected
An error occurred while saving data to or loading data from the EEPROM.
1
Load in progress
The control logic sets this bit while data is beingread from the EEPROM.
0
Save in progress
The control logic sets this bit while data is beingwritten to the EEPROM.
Table 135. SYSCLK Status
Address
Bit
Bit Name
Description
0x0D01
[7:5]
Unused
Unused.
4
Stable
The control logic sets this bit when the device considers the system clock to be
stable (see the System Clock Stability Timer section).
[3:2]
Unused
Unused.
1
Cal in progress
The control logic holds this bit set while the system clock calibrationis in progress.
0
Lock detected
Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked (or the PLL is disabled).
Register0x0D02to Register0x0D09—IRQ Monitor
If not masked via the IRQ mask register (Address 0x0209 to Address 0x0210), the appropriate IRQ monitor bit is set to a Logic 1 when the
indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0x0A04 toAddress 0x0A0B), the reset all IRQs bit
(Register 0x0A03, Bit 1), or a device reset.
Table 136. IRQ Monitor for SYSCLK
Address
Bit
Bit Name
Description
0x0D02
[7:6]
Unused
Unused.
5
SYSCLK unlocked
Indicates a SYSCLK PLL state transition from lockedto unlocked.
4
SYSCLK locked
Indicates a SYSCLK PLL state transition from unlocked to locked.
[3:2]
Unused
Unused.
1
SYSCLK cal complete
Indicates that SYSCLK calibrationis complete.
0
SYSCLK cal started
Indicates that SYSCLK calibrationhas begun.
Table 137. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address
Bit
Bit Name
Description
0x0D03
[7:4]
Unused
Unused.
3
Distributionsync
Indicates a distributionsync event.
2
Watchdog timer
Indicates expirationof the watchdog timer.
1
EEPROM fault
Indicates a fault during an EEPROM load or save operation.
0
EEPROM complete
Indicates successful completionof an EEPROM load or save operation.
Table 138. IRQ Monitor for the Digital PLL
Address
Bit
Bit Name
Description
0x0D04
7
Switching
Indicates that the DPLL is switching to a new reference.
6
Closed
Indicates that the DPLL has enteredclosed-loop operation.
5
Free run
Indicates that the DPLL has enteredfree-run mode.
4
Holdover
Indicates that the DPLL has enteredholdover mode.
3
Frequency unlocked
Indicates that the DPLL lost frequency lock.
2
Frequency locked
Indicates that the DPLL has acquired frequency lock.
1
Phase unlocked
Indicates that the DPLL lost phase lock.
0
Phase locked
Indicates that the DPLL has acquired phase lock.
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