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參數(shù)資料
| 型號(hào)： | AD9547/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 51/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9547 |
| 設(shè)計(jì)資源： | AD9547 Schematic AD9574 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9547 |
| 主要屬性： | 2 個(gè)差分式或 4 個(gè)單端輸入 |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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AD9547
Data Sheet
Rev. E | Page 50 of 104
SERIAL CONTROL PORT
M7
M0
M1
M2
M3
M4
M5
M6
13-BIT ADDRESS
SPACE
READ-ONLY
REGION
READ/WRITE
REGION
ANALOG BLOCKS AND
DIGITAL CORE
POWER-ON RESET
SERIAL CONTROL ARBITER
SPI
I2C
EEPROM
CONTROLLER
400kHz
MULTI-
FUNCTION
PIN CONTROL
LOGIC
SCLK/SCL
CS/SDA
SDIO
SDO
EEPROM
0
8300-
026
Figure 50. Serial Port Functional Diagram
The AD9547 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to many
industry-standard microcontrollers and microprocessors. The
AD9547 serial control port is compatible with most synchronous
transfer formats, including Philips I2C, Motorola SPI, and
Intel SSR protocols. The serial control port allows read/write
access to the AD9547 register map.
In SPI mode, single or multiple byte transfers are supported.
The SPI port configuration is programmable via Register 0x0000.
This register is integrated into the SPI control logic rather than
the register map and is distinct from the I2C Register 0x0000.
It is also inaccessible to the EEPROM controller.
A functional diagram of the serial control port, including its
relationship to the EEPROM, appears in Figure 50.
protocols, only one is active following power-up (as determined
by the multifunction pins, M0 to M2, during the startup sequence).
That is, the only way to change the serial port protocol is to reset
the device (or cycle the device power supply). Both protocols
use a common set of control pins as shown in Figure 51.
AD9547
SCLK/SCL
CS/SDA
SDO
SDIO
2
5
3
SERIAL
CONTROL
PORT
08300-
027
Figure 51. Serial Control Port
SPI/I2C PORT SELECTION
Because the AD9547 supports both the SPI and I2C protocols,
the active serial port protocol depends on the logic state of the
three multifunction pins, M0 to M2, at startup. If all three pins
are set to Logic 0 at startup, the SPI protocol is active. Otherwise,
the I2C protocol is active with seven different I2C slave address
settings that are based on the startup logic pattern on the M0 to
M2 pins (see Table 30). Note that the four MSBs of the slave
address are hardware coded as 1001.
Table 30. Serial Port Mode Selection
M2
M1
M0
Serial Port Mode
0
SPI
0
1
IC (address = 1001001)
0
1
0
IC (address = 1001010)
0
1
IC (address = 1001011)
1
0
IC (address = 1001100)
1
0
1
IC (address = 1001101)
1
0
IC (address = 1001110)
1
IC (address = 1001111)
SPI SERIAL PORT OPERATION
Pin Descriptions
The SCLK (serial clock) pin (SCLK/SCL) serves as the serial
shift clock. This pin is an input. SCLK synchronizes serial
control port read and write operations. The rising edge SCLK
registers write data bits, and the falling edge registers read data
bits. The SCLK pin supports a maximum clock rate of 40 MHz.
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts either as an input only (unidirectional mode) or as both
an input and an output (bidirectional mode). The AD9547
default SPI mode is bidirectional.
The SDO (serial data out) pin is useful only in unidirectional
I/O mode. It serves as the data output pin for read operations.
The CS (chip select) pin (CS/SDA) is an active low control that
gates read and write operations. This pin is internally connected
to a 30 kΩ pull-up resistor. When CS is high, the SDO and
SDIO pins go into a high impedance state.
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