參數(shù)資料
型號: ADSP-21065LKCAZ240
廠商: Analog Devices Inc
文件頁數(shù): 17/44頁
文件大?。?/td> 0K
描述: IC DSP CTLR 32BIT 196CSPBGA
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: 主機(jī)接口,串行端口
時鐘速率: 60MHz
非易失內(nèi)存: 外部
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 196-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 196-CSPBGA(15x15)
包裝: 托盤
REV. C
ADSP-21065L
–24–
Asynchronous Read/Write—Host to ADSP-21065L
Use these specifications for asynchronous host processor accesses of an ADSP-21065L, after the host has asserted
CS and HBR
(low). After the ADSP-21065L returns
HBG, the host can drive the RD and WR pins to access the ADSP-21065L’s IOP registers.
HBR and HBG are assumed low for this timing. Writes can occur at a minimum interval of (1/2) t
CK.
Parameter
Min
Max
Unit
Read Cycle
Timing Requirements:
tSADRDL
Address Setup/CS Low Before RD Low*
0.0
ns
tHADRDH
Address Hold/
CS Hold Low After RD High
0.0
ns
tWRWH
RD/WR High Width
6.0
ns
tDRDHRDY
RD High Delay After REDY (O/D) Disable
0.0
ns
tDRDHRDY
RD High Delay After REDY (A/D) Disable
0.0
ns
Switching Characteristics:
tSDATRDY
Data Valid Before REDY Disable from Low
1.5
ns
tDRDYRDL
REDY (O/D) or (A/D) Low Delay After
RD Low
13.5
ns
tRDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read
28.0 + DT
ns
tHDARWH
Data Disable After
RD High
2.0
10.0
ns
Write Cycle
Timing Requirements:
tSCSWRL
CS Low Setup Before WR Low
0.0
ns
tHCSWRH
CS Low Hold After WR High
0.0
ns
tSADWRH
Address Setup Before
WR High
5.0
ns
tHADWRH
Address Hold After
WR High
2.0
ns
tWWRL
WR Low Width
7.0
ns
tWRWH
RD/WR High Width
6.0
ns
tDWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable
0.0
ns
tSDATWH
Data Setup Before
WR High
5.0
ns
tHDATWH
Data Hold After
WR High
1.0
ns
Switching Characteristics:
tDRDYWRL
REDY (O/D) or (A/D) Low Delay After
WR/CS Low
13.5
ns
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write
7.75
ns
NOTE
*Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR23-0 must be a nonMMS value 1/2 tCLK before
RD or WR goes low or by t
HBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See Host Inter-
face, in the ADSP-21065L SHARC User’s Manual, Second Edition.
相關(guān)PDF資料
PDF描述
ASM24DTBH-S189 CONN EDGECARD 48POS R/A .156 SLD
GEC08DREN-S13 CONN EDGECARD 16POS .100 EXTEND
AGM24DTBH-S189 CONN EDGECARD 48POS R/A .156 SLD
AYM24DTBD-S189 CONN EDGECARD 48POS R/A .156 SLD
ASM24DTBD-S189 CONN EDGECARD 48POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21065LKCAZ-240 制造商:Analog Devices 功能描述:DSP SEMICONDUCTOR ((NS))
ADSP-21065LKCAZ240 制造商:Analog Devices 功能描述:IC 32-BIT DSP
ADSP-21065LKCAZ264 功能描述:IC DSP CTLR 32BIT 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號處理器) 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI,以太網(wǎng),RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSP-21065LKS-240 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 60MHz 60MIPS 208-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:ADSP-21065 60 MHZ - Bulk 制造商:Analog Devices 功能描述:IC SHARC DSP 60MHZ 21065 MQFP208
ADSP-21065LKS-264 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 66MHz 66MIPS 208-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:ADSP-21065L 66 MHZ COMMERCIAL GRADE - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NS))