參數(shù)資料
型號(hào)： ADSP-21065LKCAZ240
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 21/44頁(yè)
文件大小： 0K
描述： IC DSP CTLR 32BIT 196CSPBGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 60MHz
非易失內(nèi)存： 外部
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 196-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 196-CSPBGA（15x15）
包裝： 托盤(pán)
REV. C
ADSP-21065L
–28–
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand-
shake mode,
DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled
by the ADDR23-0, RD, WR, SW, MS3-0, ACK, and DMAG signals. External mode cannot be used for transfers with SDRAM. For
Paced Master mode, the data transfer is controlled by ADDR23-0, RD, WR, MS3-0, and ACK (not DMAG). For Paced Master mode,
the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR23-0, RD, WR, MS3-0, SW, DATA31-0, and ACK also apply.
Parameter
Min
Max
Unit
Timing Requirements:
tSDRLC
DMARx Low Setup Before CLKIN1
5.0
ns
tSDRHC
DMARx High Setup Before CLKIN1
5.0
ns
tWDR
DMARx Width Low (Nonsynchronous)
6.0
ns
tSDATDGL
Data Setup After
DMAGx Low2
15.0 + 20 DT
ns
tHDATIDG
Data Hold After
DMAGx High
0.0
ns
tDATDRH
Data Valid After
DMARx High2
25.0 + 14 DT
ns
tDMARLL
DMARx Low Edge to Low Edge
18.0 + 14 DT
ns
tDMARH
DMARx Width High
6.0
ns
Switching Characteristics:
tDDGL
DMAGx Low Delay After CLKIN
14.0 + 10 DT
20.0 + 10 DT
ns
tWDGH
DMAGx High Width
10.0 + 12 DT + HI
ns
tWDGL
DMAGx Low Width
16.0 + 20 DT
ns
tHDGC
DMAGx High Delay After CLKIN
0.0 – 2 DT
6.0 – 2 DT
ns
tDADGH
Address Select Valid to
DMAGx High
28.0 + 16 DT
ns
tDDGHA
Address Select Hold After
DMAGx High
–1.0
ns
tVDATDGH
Data Valid Before
DMAGx High3
16.0 + 20 DT
ns
tDATRDGH
Data Disable After
DMAGx High4
0.0
4.0
ns
tDGWRL
WR Low Before DMAGx Low
5.0 + 6 DT
8.0 + 6 DT
ns
tDGWRH
DMAGx Low Before WR High
18.0 + 19 DT + W
ns
tDGWRR
WR High Before DMAGx High
0.75 + 1 DT
3.0 + 1 DT
ns
tDGRDL
RD Low Before DMAGx Low
5.0
8.0
ns
tDRDGH
RD Low Before DMAGx High
24.0 + 26 DT + W
ns
tDGRDR
RD High Before DMAGx High
0.0
2.0
ns
tDGWR
DMAGx High to WR, RD Low
5.0 + 6 DT + HI
ns
W = (number of wait states specified in WAIT register)
tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1Only required for recognition in the current cycle.
2t
SDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven tDATDRH after DMARx is brought high.
3t
VDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 8 + 9 DT + (n
tCK) where n
equals the number of extra cycles that the access is prolonged.
4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
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