參數(shù)資料
型號： ADSP-21065LKCAZ240
廠商： Analog Devices Inc
文件頁數(shù)： 4/44頁
文件大小： 0K
描述： IC DSP CTLR 32BIT 196CSPBGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點
接口： 主機接口，串行端口
時鐘速率： 60MHz
非易失內(nèi)存： 外部
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 196-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 196-CSPBGA（15x15）
包裝： 托盤
REV. C
–12–
ADSP-21065L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Test
C Grade
K Grade
Parameter
Conditions
Min
Max
Min
Max
Unit
VDD
Supply Voltage
3.13
3.60
3.13
3.60
V
TCASE
Case Operating Temperature
–40
+100
0
+85
∞C
VIH
High Level Input Voltage
@ VDD = max
2.0
VDD + 0.5
2.0
VDD + 0.5
V
VIL1
Low Level Input Voltage1
@ VDD = min
–0.5
0.8
–0.5
0.8
V
VIL2
Low Level Input Voltage
2
@ VDD = min
–0.5
0.7
–0.5
0.7
V
NOTE
See Environmental Conditions for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
C and K Grades
Parameter
Test Conditions
Min
Max
Unit
VOH
High Level Output Voltage
3
@ VDD = min, IOH = –2.0 mA
4
2.4
V
VOL
Low Level Output Voltage
3
@ VDD = min, IOL = 4.0 mA
4
0.4
V
IIH
High Level Input Current
5
@ VDD = max, VIN = VDD max
10
mA
IIL
Low Level Input Current
5
@ VDD = max, VIN = 0 V
10
mA
IILP
Low Level Input Current
6
@ VDD = max, VIN = 0 V
150
mA
IOZH
Three-State Leakage Current
7, 8, 9, 10
@ VDD = max, VIN = VDD max
10
mA
IOZL
Three-State Leakage Current
7
@ VDD = max, VIN = 0 V
8
mA
IOZLS
Three-State Leakage Current
8
@ VDD = max, VIN = 0 V
150
mA
IOZLA
Three-State Leakage Current
11
@ VDD = max, VIN = 1.5 V
350
mA
IOZLAR
Three-State Leakage Current
10
@ VDD = max, VIN = 0 V
4
mA
IOZLC
Three-State Leakage Current
9
@ VDD = max, VIN = 0 V
1.5
mA
CIN
Input Capacitance
12, 13
fIN = 1 MHz, TCASE = 25
∞C, VIN = 2.5 V
8
pF
NOTES
1 Applies to input and bidirectional pins: DATA
31-0, ADDR23-0, BSEL, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG11-0, HBG, CS, DMAR1, DMAR2, BR2-1, ID2-0,
RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1, RESET, TRST,
PWM_EVENT0, PWM_EVENT1,
RAS, CAS, SDWE, SDCKE.
2 Applies to input pin CLKIN.
3 Applies to output and bidirectional pins: DATA
31-0, ADDR23-0, MS3-0, RD, WR, SW, ACK, FLAG11-0, HBG, REDY, DMAG1, DMAG2, BR2-1, CPA, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL,
BMS, TDO, EMU, BMSTR, PWM_EVENT0, PWM_EVENT1,
RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10.
4 See Output Drive Currents for typical drive current capabilities.
5 Applies to input pins: ACK,
SBTS, IRQ
2-0, HBR, CS, DMAR1, DMAR2, ID1-0, BSEL, CLKIN, RESET, TCK (Note that ACK is pulled up internally with 2 k
W
during reset in a multiprocessor system, when ID1-0 = 01 and another ADSP-21065L is not requesting bus mastership.)
6Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B,
TRST, TMS, TDI.
7Applies to three-statable pins: DATA
31-0, ADDR23-0, MS3-0, RD, WR, SW, ACK, FLAG11-0, REDY, HBG, DMAG1, DMAG2, BMS, TDO, RAS, CAS, DQM,
SDWE, SDCLK0, SDCLK1, SDCKE, SDA10, and EMU (Note that ACK is pulled up internally with 2 k
W during reset in a multiprocessor system, when ID1-0 =
01 and another ADSP-21065L is not requesting bus mastership).
8 Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1.
9Applies to
CPA pin.
10Applies to ACK pin when pulled up.
11 Applies to ACK pin when keeper latch enabled.
12 Guaranteed but not tested.
13 Applies to all signal pins.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130
∞C
Storage Temperature Range . . . . . . . . . . . . . –65
∞C to +150∞C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . . 280
∞C
*Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21065L features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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