- 您現(xiàn)在的位置：買賣IC網 > PDF目錄19464 > ADSP-21065LKCAZ240 (Analog Devices Inc)IC DSP CTLR 32BIT 196CSPBGA PDF資料下載
參數資料
| 型號： | ADSP-21065LKCAZ240 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 42/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CTLR 32BIT 196CSPBGA |
| 產品培訓模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 60MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-BGA，CSPBGA |
| 供應商設備封裝： | 196-CSPBGA（15x15） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁第43頁第44頁
REV. C
ADSP-21065L
–7–
PIN DESCRIPTIONS
ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to
CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN
(or to TCK for
TRST).
Unused inputs should be tied or pulled to VDD or GND, except for ADDR23-0, DATA31-0, FLAG11-0, SW, and inputs that have
internal pull-up or pull-down resistors (
CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI)—these pins can be left float-
ing. These pins have a logic-level hold circuit that prevents the input from floating internally.
I = Input
S = Synchronous
P = Power Supply
(O/D) = Open Drain
O = Output
A = Asynchronous
G = Ground
(A/D) = Active Drive
T = Three-state (when
SBTS is asserted, or when the ADSP-2106x is a bus slave)
Pin
Type
Function
ADDR23-0
I/O/T
External Bus Address. The ADSP-21065L outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system the bus master outputs addresses for read/
writes of the IOP registers of the other ADSP-21065L. The ADSP-21065L inputs addresses
when a host processor or multiprocessing bus master is reading or writing its IOP registers.
DATA31-0
I/O/T
External Bus Data. The ADSP-21065L inputs and outputs data and instructions on these
pins. The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-
point data over bits 31-0. 16-bit short word data is transferred over bits 15-0 of the bus. Pull-up
resistors on unused DATA pins are not necessary.
MS
3-0
I/O/T
Memory Select Lines. These lines are asserted as chip selects for the corresponding banks of
external memory. Internal ADDR25-24 are decoded into MS3-0. The MS3-0 lines are decoded
memory address lines that change at the same time as the other address lines. When no external
memory access is occurring the
MS
3-0 lines are inactive; they are active, however, when a condi-
tional memory access instruction is executed, whether or not the condition is true. Additionally,
an
MS
3-0 line which is mapped to SDRAM may be asserted even when no SDRAM access is
active. In a multiprocessor system, the
MS
3-0 lines are output by the bus master.
RD
I/O/T
Memory Read Strobe. This pin is asserted when the ADSP-21065L reads from external memory
devices or from the IOP register of another ADSP-21065L. External devices (including another
ADSP-21065L) must assert
RD to read from the ADSP-21065L’s IOP registers. In a multipro-
cessor system,
RD is output by the bus master and is input by another ADSP-21065L.
WR
I/O/T
Memory Write Strobe. This pin is asserted when the ADSP-21065L writes to external memory
devices or to the IOP register of another ADSP-21065L. External devices must assert
WR to
write to the ADSP-21065L’s IOP registers. In a multiprocessor system,
WR is output by the bus
master and is input by the other ADSP-21065L.
SW
I/O/T
Synchronous Write Select. This signal interfaces the ADSP-21065L to synchronous memory
devices (including another ADSP-21065L). The ADSP-21065L asserts
SW to provide an early
indication of an impending write cycle, which can be aborted if
WR is not later asserted (e.g., in
a conditional write instruction). In a multiprocessor system,
SW is output by the bus master and
is input by the other ADSP-21065L to determine if the multiprocessor access is a read or write.
SW is asserted at the same time as the address output.
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold
off completion of an external memory access. The ADSP-21065L deasserts ACK as an output
to add wait states to a synchronous access of its IOP registers. In a multiprocessor system, a
slave ADSP-21065L deasserts the bus master’s ACK input to add wait state(s) to an access of
its IOP registers. The bus master has a keeper latch on its ACK pin that maintains the input at
the level to which it was last driven.
SBTS
I/S
Suspend Bus Three-State. External devices can assert
SBTS to place the external bus address,
data, selects, and strobes—but not SDRAM control pins—in a high impedance state for the
following cycle. If the ADSP-21065L attempts to access external memory while
SBTS is as-
serted, the processor will halt and the memory access will not finish until
SBTS is deasserted.
SBTS should only be used to recover from host processor/ADSP-21065L deadlock.
IRQ
2-0
I/A
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG11-0
I/O/A
Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can
be tested as a condition. As an output, it can be used to signal external peripherals.
相關PDF資料 |
PDF描述 |
|---|---|
| ASM24DTBH-S189 | CONN EDGECARD 48POS R/A .156 SLD |
| GEC08DREN-S13 | CONN EDGECARD 16POS .100 EXTEND |
| AGM24DTBH-S189 | CONN EDGECARD 48POS R/A .156 SLD |
| AYM24DTBD-S189 | CONN EDGECARD 48POS R/A .156 SLD |
| ASM24DTBD-S189 | CONN EDGECARD 48POS R/A .156 SLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21065LKCAZ-240 | 制造商:Analog Devices 功能描述:DSP SEMICONDUCTOR ((NS)) |
| ADSP-21065LKCAZ240 | 制造商:Analog Devices 功能描述:IC 32-BIT DSP |
| ADSP-21065LKCAZ264 | 功能描述:IC DSP CTLR 32BIT 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21065LKS-240 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 60MHz 60MIPS 208-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:ADSP-21065 60 MHZ - Bulk 制造商:Analog Devices 功能描述:IC SHARC DSP 60MHZ 21065 MQFP208 |
| ADSP-21065LKS-264 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 66MHz 66MIPS 208-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:ADSP-21065L 66 MHZ COMMERCIAL GRADE - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NS)) |
發(fā)布緊急采購，3分鐘左右您將得到回復。