tSDRLC DMARx DATA (FROM ADSP-2106x TO EXTERNAL DEVICE) DATA (FROM EXTERNAL" />
參數(shù)資料
型號(hào): ADSP-21065LKCAZ240
廠商: Analog Devices Inc
文件頁數(shù): 22/44頁
文件大?。?/td> 0K
描述: IC DSP CTLR 32BIT 196CSPBGA
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: 主機(jī)接口,串行端口
時(shí)鐘速率: 60MHz
非易失內(nèi)存: 外部
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 196-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 196-CSPBGA(15x15)
包裝: 托盤
REV. C
ADSP-21065L
–29–
CLKIN
tSDRLC
DMARx
DATA (FROM
ADSP-2106x TO
EXTERNAL DEVICE)
DATA (FROM
EXTERNAL DEVICE
TO ADSP-2106x)
RD
(EXTERNAL
MEMORY TO
EXTERNAL DEVICE)
WR
(EXTERNAL DEVICE
TO EXTERNAL
MEMORY)
tWDR
tSDRHC
tDMARH
tDMARLL
tHDGC
tWDGH
tDDGL
tWDGL
DMAGx
tVDATDGH
t DATDRH
t DATRDGH
tHDATIDG
tDGWRL
t DGWRH
tDGWRR
tDGRDL
tDRDGH
tDGRDR
t SDATDGL
*“MEMORY READ – BUS MASTER,” “MEMORY WRITE – BUS MASTER,” AND “SYNCHRONOUS READ/WRITE – BUS MASTER”
TIMING SPECIFICATIONS FOR ADDR23–0, RD, WR, SW, MS3–0, AND ACK ALSO APPLY HERE.
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY (EXTERNAL HANDSHAKE MODE)
tDDGHA
ADDRESS
SW, MSx
tDADGH
*
Figure 18. DMA Handshake Timing
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ADSP-21065LKCAZ-240 制造商:Analog Devices 功能描述:DSP SEMICONDUCTOR ((NS))
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