參數(shù)資料
型號(hào)： ADV7183AKST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： LEAD FREE, MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 16/104頁(yè)
文件大?。?/td> 894K
代理商： ADV7183AKST
ADV7183A
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
Rev. A | Page 16 of 104
POWER-SAVE MODES
Power-Down
PDBP, Address 0x0F, [2]
There are two ways to shut down the digital core of the
ADV7183A: a pin (PWRDN) and a bit (PWRDN see below).
The PDBP controls which of the two has the higher priority.
The default is to give the pin (PWRDN) priority. This allows the
user to have the ADV7183A powered down by default.
Table 11. PDBP Function
PDBP
Description
0*
Digital core power controlled by the PWRDN pin (bit is
disregarded).
1
Bit has priority (pin is disregarded).
*Default value.
PWRDN, Address 0x0F, [5]
Setting the PWRDN bit switches the ADV7183A into a chip-
wide power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
operation. No I
2
C bits are lost during power-down. The
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I
2
C interface itself is unaffected,
and remains operational in power-down mode.
The ADV7183A leaves the power-down state if the PWRDN bit
is set to 0 (via I
2
C), or if the overall part is reset using Pin
RESET.
Note that PDBP must be set to 1 for the PWRDN bit to power
down the ADV7183A.
Table 12. PWRDN Function
PWRDN
Description
0*
Chip operational.
1
ADV7183A in chip-wide power-down.
*Default value.
ADC Power-Down Control
The ADV7183A contains three 10-bit ADCs (ADC 0, ADC 1,
and ADC 2). If required, it is possible to power down each ADC
individually.
When should the ADCs be powered down
CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
S-Video mode. ADC 2 should be powered down to save on
power consumption.
PWRDN_ADC_0, Address 0x3A, [3]
Table 13. PWRDN_ADC_0 Function
PWRDN_ADC_0
0*
1
*Default value.
Description
ADC normal operation.
Power down ADC 0.
PWRDN_ADC_1, Address 0x3A, [2]
Table 14. PWRDN_ADC_1 Function
PWRDN_ADC_1
Description
0*
ADC normal operation.
1
Power down ADC 1.
*Default value.
PWRDN_ADC_2, Address 0x3A, [1]
Table 15. PWRDN_ADC_2 Function
PWRDN_ADC_2
0*
1
*Default value.
RESET CONTROL
Description
ADC normal operation.
Power down ADC 2.
Chip Reset (RES), Address 0x0F, [7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7183A, issues a full chip reset. All I
2
C registers get reset to
their default values
6
. After the reset sequence, the part immedi-
ately starts to acquire the incoming video signal.
Notes
After setting the RES bit (or initiating a reset via the pin),
the part returns to the default mode of operation with
respect to its primary mode of operation. All I
2
C bits are
loaded with their default values, making this bit self-
clearing.
Executing a software reset takes approximately 2 ms.
However, it is recommended to wait 5 ms before any
further I
2
C writes are performed.
The I
2
C master controller receives a no acknowledge
condition on the ninth clock cycle when Chip Reset is
implemented. See the MPU Port Description section.
Table 16. RES Function
RES
Description
0*
Normal operation.
1
Start reset sequence.
*Default value.
6
Some register bits do not have a reset value specified. They keep their last
written value. Those bits are marked as having a reset value of x in the
register table.
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