參數(shù)資料
型號(hào)： ADV7183AKST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： LEAD FREE, MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 75/104頁(yè)
文件大?。?/td> 894K
代理商： ADV7183AKST
ADV7183A
Table 180. Register 0x09 to 0x0E
Subaddress
Register
0x09
(Saturation)
0x0A
Register
Rev. A | Page 75 of 104
Bit Description
Reserved
Bit
4
0
0
Register Setting
Comments
0x00 = 0IRE;
0x7F = 100IRE;
0xFF = –100IRE
Hue range =
–90° to +90°
7
1
0
6
0
0
5
0
0
3
0
0
2
0
0
1
0
0
0
0
0
Reserved
Brightness
BRI[7:0]
. This register controls
the brightness of the video
signal.
HUE[7:0]
. This register
contains the value for the color
hue adjustment.
DEF_VAL_EN
. Default value
enable.
0x0B
0
0
0
0
0
0
0
0
Hue Register
0x0C
Default Value Y
0
Free Run mode
dependent on
DEF_VAL_AUTO_EN
Force SDP Free Run
mode on and output
blue screen
Disable SDP Free Run
mode
Enable Automatic Free
Run mode (blue
screen)
1
0
DEF_VAL_AUTO_EN
. Default
value.
1
When lock is lost,
Free Run mode
can be enabled
to output stable
timing, clock,
and a set color.
Default Y value
output in free-
run mode.
0
0
1
1
0
1
Y[7:0] = {DEF_Y[5:0],
0, 0, 0, 0}
Cr[7:0] = {DEF_C[7:4],
0, 0, 0, 0, 0, 0}
Cb[7:0] = {DEF_C[3:0],
0, 0, 0, 0, 0, 0}
DEF_Y[5:0]
. Default value Y.
This register holds the Y
default value.
0x0D
Default Value C
DEF_C[7:0].
Default value C. Cr
and Cb default values are
defined in this register.
0
1
1
1
1
1
0
0
Default Cb/Cr
value output in
Free Run mode.
Default values
give blue screen
output.
0x0E
ADI Control
0
0
Low drive strength
(1×)
Medium-low (2×)
Medium-high (3×)
High drive strength
(4×)
Low drive strength
(1×)
Medium-low (2×)
Medium-high (3×)
High drive strength
(4×)
Set as default
LLC pin active
LLC pin drivers three-
stated
Set as default
0
1
1
1
0
1
DR_STR_S[1:0]
. Select the
drive strength of the sync
signals. HS, VS, and F can be
increased or decreased for
EMC or crosstalk reasons.
0
0
0
1
1
1
0
1
DR_STR_C[1:0]
. Select the
strength of the clock signal
output driver. Can be
increased or decreased for
EMC or crosstalk reasons.
0
1
0
0
See TOD
(
Table 177
);
TIM_OE
(
Table 178
).
Reserved
TRI_LLC
. Enables the LLC pin
to be three-stated.
0
Reserved
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