參數(shù)資料
型號(hào)： ADV7183AKST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： LEAD FREE, MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 51/104頁(yè)
文件大?。?/td> 894K
代理商： ADV7183AKST
ADV7183A
PVENDDELE PAL VSync End Delay on Even Field,
Address 0xE9,[6]
Table 129. PVENDDELE Function
PVENDDELE
Description
0*
No delay.
1
Delay VSync going low on an even field by a line
relative to PVEND.
*Default value.
Rev. A | Page 51 of 104
PVENDSIGN PAL VSync End Sign, Address 0xE9, [5]
Table 130. PVENDSIGN Function
PVENDSIGN
Description
0*
Delay end of VSync. Set for user manual
programming.
1
Advance end of VSync. Not recommended for
user programming.
*Default value.
PVEND[4:0] PAL Vsync End, Address 0xE9,[4:0]
Table 131. PVEND Function
PVEND
Description
10100*
PAL VSync end position.
*Default value.
Note: For all NTSC/PAL VSync timing controls, both the V bit
in the AV code and the VSync on the VS pin are modified.
PFTOGDELO PAL Field Toggle Delay on Odd Field,
Address 0xEA, [7]
Table 132. PFTOGDELO Function
PFTOGDELO
Description
0*
No delay.
1
Delay F toggle/transition on an odd field by a
line relative to PFTOG.
*Default value.
PFTOGDELE PAL Field Toggle Delay on Even Field,
Address 0xEA [6]
Table 133. PFTOGDELE Function
PFTOGDELE
Description
0
No delay.
1*
Delay F toggle/transition on an even field by a
line relative to PFTOG.
*Default value.
PFTOGSIGN PAL Field Toggle Sign, Address 0xEA, [5]
Table 134. PFTOGSIGN Function
PFTOGSIGN
Description
0
Delay Field transition. Set for user manual
programming.
1*
Advance Field transition. Not recommended for
user programming.
*Default value.
PFTOG PAL Field Toggle, Address 0xEA [4:0]
Table 135. PFTOG Function
PFTOG
Description
00011*
PAL Field toggle position.
*Default value.
For all NTSC/PAL Field timing controls, the F bit in the AV
code and the Field signal on the FIELD/DE pin are modified.
0
ADVANCE TOGGLE OF
FIELD BY PTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
PFTOGSIGN
ODD FIELD
0
1
NO
YES
PFTOGDELE
ADDITIONAL
DELAY BY
1 LINE
1
0
PFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
1
0
FIELD
TOGGLE
NOT VALID FOR USER
PROGRAMMING
Figure 30. PAL F Toggle
SDP SYNC PROCESSING
The ADV7183A has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I
2
C bits.
ENHSPLL Enable HSync Processor (SDP), Address 0x01, [6]
The HSYNC processor is designed to filter incoming HSyncs
that have been corrupted by noise, providing improved per-
formance for video signals with stable time bases but poor SNR.
For CVBS PAL/NTSC, YC PAL/NTSC enable the HSync
processor. For SECAM disable the HSync Processor. For YPrPb
through SDP, disable HSYNC Processor.
Table 136. ENHSPLL Function
ENHSPLL
Description
0
Disable the HSync processor.
1*
Enable the HSync processor.
*Default value.
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