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參數(shù)資料
| 型號： | AM79C940 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁數(shù)： | 38/122頁 |
| 文件大小： | 914K |
| 代理商： | AM79C940 |
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AMD
38
Am79C940
Parameter
1. Parallel Resonant Frequency
2. Resonant Frequency Error
(CL = 20 pF)
3. Change in Resonant Frequency
With Respect To Temperature (CL = 20 pF)*
4. Crystal Capacitance
5. Motional Crystal Capacitance (C1)
6. Series Resistance
7. Shunt Capacitance
Min
Nom
20
Max
Units
MHz
–50
+50
PPM
–40
+40
20
PPM
pF
pF
ohm
pF
0.022
35
7
* Requires trimming crystal spec; no trim is 50 ppm total
External Clock Drive Characteristics
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than
±
0.5 ns jitter at DO
±
.
Clock Frequency:
20 MHz
±
0.01%
< 6 ns from 0.5 V
to V
DD
–0.5
Rise/Fall Time (tR/tF):
XTAL1 HIGH/LOW Time
(tHIGH/tLOW):
40 – 60%
duty cycle
XTAL1 Falling Edge to
Falling Edge Jitter:
<
±
0.2 ns at
2.5 V input (V
DD
/2)
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO
±
) are de-
signed to operate into terminated transmission lines.
When operating into a 78 ohm terminated transmission
line, signaling meets the required output levels and
skew for Cheapernet, Ethernet and IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental mode crystal oscillator provides
the basic timing reference for the SIA portion of the
MACE device. It is divided by two, to create the internal
transmit clock reference. Both clocks are fed into the
SIA’s Manchester Encoder to generate the transitions in
the encoded data stream. The internal transmit clock is
used by the SIA to internally synchronize the Internal
Transmit Data (ITXD) from the controller and Internal
Transmit Enable (ITENA). The internal transmit clock is
also used as a stable bit rate clock by the receive section
of the SIA and controller.
The oscillator requires an external 0.005% crystal, or an
external 0.01% CMOS-level input as a reference. The
accuracy requirements if an external crystal is used are
tighter because allowance for the on-chip oscillator
must be made to deliver a final accuracy of 0.01%.
Transmission is enabled by the controller. As long as the
ITENA request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO
±
. When the internal request is dropped by the con-
troller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
TSEL LOW:
The idle state of DO
±
yields “zero”
differential to operate transformer-
coupled loads.
TSEL HIGH:
In this idle state, DO+ is positive
with respect to DO– (logical\HIGH).
Receive Path
The principal functions of the Receiver are to signal the
MACE device that there is information on the receive
pair, and separate the incoming Manchester encoded
data stream into clock and NRZ data.
The Receiver section (see Receiver Block Diagram)
consists of two parallel paths. The receive data path is a
zero threshold, wide bandwidth line receiver. The carrier
path is an offset threshold bandpass detecting line re-
ceiver. Both receivers share common bias networks to
allow operation over a wide input common mode range.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C940_00 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940-16/25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| AM79C940-16JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940AVC | 制造商:AMD 功能描述:79C940 AMD'94 SMT N6E2A |
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