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| 型號(hào)： | AM79C940 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁(yè)數(shù)： | 68/122頁(yè) |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940 |
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AMD
68
Am79C940
not implement Link Test, this
function can be disabled by set-
ting the DLNKTST bit. With Link
Test disabled (DLNKTST = 1),
the data driver, receiver and
loopback functions as well as col-
lision detection remain enabled
irrespective of the presence or
absence of data or link pulses on
the RXD
±
pair. The transmitter
will continue to generate link beat
pulses during periods of transmit
data inactivity. Set by hardware
or software reset.
Disable Link Test. When set, the
integrated
10BASE-T
ceiver will be forced into the link
pass state, regardless of receive
link test pulses or receive packet
activity.
Reversed Polarity. Indicates the
receive polarity of the RD
±
pair.
When normal polarity is de-
tected, the REVPOL bit will be
cleared, and the
RXPOL
pin (ca-
pable of driving a Polarity OK
LED) will be driven LOW. When
reverse polarity is detected, the
REVPOL bit will be set, and the
RXPOL
pin should be externally
pulled HIGH.
Disable Auto Polarity Correction.
When set, the automatic polarity
correction will be disabled. Polar-
ity detection and indication will
still be possible via the
RXPOL
pin.
Low Receive Threshold. When
set, the threshold of the twisted
pair receiver will be reduced by
4.5 dB, to allow extended dis-
tance operation.
Auto Select. When set, the
PORTSEL [1–0] bits are overrid-
den, and the MACE device will
automatically select the operat-
ing media interface port. When
the 10BASE-T transceiver is in
the link pass state (due to receiv-
ing valid packet data and/or Link
Test pulses or the DLNKTST bit
is set), the 10BASE-T port will be
used. When the 10BASE-T port
is in the link fail state, the AUI port
will be used. Switching between
the ports will not occur during
transmission in order to avoid
any type of fragment generation.
Remote Wake. When set prior to
the
SLEEP
pin being activated,
the AUI and 10BASE-T receiver
sections and the EADI port
will
Bit 6
DLNKTST
trans-
Bit 5
REVPOL
Bit 4
DAPC
Bit 3
LRT
Bit 2
ASEL
Bit 1
RWAKE
continue to operate even during
SLEEP
. Incoming packet activity
will be passed to the EADI port
pins permitting detection of spe-
cific frame contents used to
initiate a wake-up sequence.
RWAKE must be programmed
prior to
SLEEP
being asserted
for this function to operate.
RWAKE is not cleared by
SLEEP
, only by activation of the
SWRST bit or
RESET
pin.
Auto Wake. When set prior to the
SLEEP
pin being activated, the
10BASE-T receiver section will
continue to operate even during
SLEEP
, and will activate the
LNKST
pin if Link Pass is de-
tected. AWAKE must be pro-
grammed prior to
SLEEP
being
asserted for this function to oper-
ate. AWAKE is not cleared by
SLEEP
, only by activation of the
SWRST bit or
RESET
pin.
Bit 0
AWAKE
Chip Identification Register
(CHIPID [15–00])
This 16-bit value corresponds to the specific version of
the MACE device being used. The value will be pro-
grammed to X940h, where Xis a value dependent on
version.
(REG ADDR 16 &17)
CHIPID [07–00]
CHIPID [15–08]
Internal Address
Configuration (IAC)
This register allows access to and from the multi-byte
Physical Address and Logical Address Filter locations,
using only a single byte location.
(REG ADDR 18)
The MACE device will reset the IAC register PHYADDR
and LOGADDR bits after the appropriate number of
read or write cycles have been executed on the Physical
Address Register or the Logical Address Filter. Once
the LOGADDR bit is set, the MACE device will reset the
bit after 8 read or write operations have been performed.
Once the PHYADDR bit is set, the MACE device will re-
set the bit after 6 read or write operations have been per-
formed. The MACE device makes no distinction
between read or write operations, advancing the inter-
nal address RAM pointer with each access. If both
PHYADDR and LOGADDR bits are set, the MACE de-
vice will accept only the LOGADDR bit. If the PHYADDR
bit is set and the Logical Address Filter location is ac-
cessed, a
DTV
will not be returned. Similarly, if the
LOGADDR bit is set and the Physical Address Register
location is accessed,
DTV
will not be returned.
PHYADDR or LOGADDR can be set in the same cycle
as ADDRCHG.
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| AM79C940JCW | Media Access Controller for Ethernet (MACE) |
| AM79C940KCW | Media Access Controller for Ethernet (MACE) |
| AM79C960 | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KC | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C940_00 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940-16/25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| AM79C940-16JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940AVC | 制造商:AMD 功能描述:79C940 AMD'94 SMT N6E2A |
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