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| 型號(hào)： | AM79C940 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問(wèn)控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁(yè)數(shù)： | 45/122頁(yè) |
| 文件大小： | 914K |
| 代理商： | AM79C940 |
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AMD
45
Am79C940
Internal/External Address Recognition Capabilities
PROM
M/
R
X
0
EAM/R
X
H
↓
H
↓
Required Timing
Received Messages
All Received Frames
All Received Frames
1
0
No timing requirements
No timing requirements
0
0
0
1
Low for 200 ns within 512-bits after SFD
No timing requirements
Physical/Logical/Broadcast Matches
Physical/Logical/Broadcast Matches
0
1
Low for 200 ns within 8-bits after DA field
All Received Frames
General Purpose Serial Interface (GPSI)
The GPSI port provides the signals necessary to pre-
sent an interface consistent with the non encoded data
functions observed to/from a LAN controller such as the
Am7990 Local Area Network Controller for Ethernet
(LANCE). The actual GPSI pins are functionally identi-
cal to some of the pins from the DAI and the EADI ports,
the GPSI replicates this type of interface.
The GPSI allows use of an external Manchester en-
coder/decoder, such as the Am7992B Serial Interface
Adapter (SIA). In addition, it allows the MACE device to
be used as a MAC sublayer engine in a repeater based
on the Am79C980 Integrated Multiport Repeater (IMR).
Simple connection to the IMR Expansion Bus allows the
MAC to view all packet data passing through a number
of interconnected IMRs, allowing statistics and network
management information to be collected.
The GPSI functional pins are duplicated as follows:
Pin Configuration for GPSI Function
LANCE
Pin
RX
RCLK
RENA
CLSN
TX
TCK
TENA
MACE
Pin
RXDAT
SRDCLK
RXCRS
CLSN
TXDAT+
STDCLK
TXEN
Function
Receive Data
Receive Clock
Receive Carrier Sense
Collision
Transmit Data
Transmit Clock
Transmit Enable
Type
I
I
I
I
O
I
O
IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board level continuity test and diag-
nostics. All digital input, output and input/output and in-
put/output pins are tested. Analog pins, including the
AUI differential driver (DO
±
) and receivers DI
±
, CI
±
),
and the crystal input (XTAL1/XTAL2) pins, are not
tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the MACE de-
vice. For additional details, consult the IEEE Standard
Test Access Port and Boundary-Scan Architecture
document (IEEE Std 1149.1–1990).
The boundary scan test circuit requires four pins (TCK,
TMS, TDI and TDO ), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an in-
struction register, a data register array and a power on
reset circuit. Internal pull-up resistors are provided for
the TCK, TDI and TMS pins.
The TAP engine is a 16 state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. An
independent power on reset circuit is provided to ensure
the FSM is in the TEST_LOGIC_RESET state at
power up.
In addition to the minimum IEEE 1149.1 instruction re-
quirements (EXTEST, SAMPLE and BYPASS), three
additional instructions (IDCODE, TRI_ST and SET_I/O)
are provided to further ease board level testing. All
unused instruction codes are reserved.
IEEE 1149.1 Supported Instruction Summary
Inst
Name
Selected
Data Reg
Reg
Mode
Inst
Code
Description
EXTEST External Test
BSR
Test
0000
IDCode
ID Code Inspection
ID Reg
Normal
0001
Sample
Sample Boundary
BSR
Normal
0010
TRI_ST
Force Tristate
Bypass
Normal
0011
SET_I/0 Control BoundaryToI/0
Bypass
Test
0100
Bypass
Bypass Scan
Bypass
Normal
1111
After hardware or software reset, the IDCODE instruc-
tion is always invoked. The decoding logic provides sig-
nals to control the data flow in the DATA registers
according to the current instruction.
Each Boundary Scan Register (BSR) cell also has two
stages. A flip-flop and a latch are used in the SERIAL
SHIFT STAGE and the PARALLEL OUTPUT STAGE
respectively.
There are four possible operational modes in the BSR
cell:
(1) CAPTURE
(2) SHIFT
(3) UPDATE
(4) SYSTEM FUNCTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C940JCW | Media Access Controller for Ethernet (MACE) |
| AM79C940KCW | Media Access Controller for Ethernet (MACE) |
| AM79C960 | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KC | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C940_00 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940-16/25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| AM79C940-16JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940AVC | 制造商:AMD 功能描述:79C940 AMD'94 SMT N6E2A |
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