參數(shù)資料
型號： AMIS49587GEVK
廠商： ON Semiconductor
文件頁數(shù)： 11/55頁
文件大小： 0K
描述： KIT EVALUATION AMIS49587
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，電源線路收發(fā)器
嵌入式： 否
已用 IC / 零件： AMIS49587
已供物品： 2 個(gè)板，線纜，CD，文檔
其它名稱： AMIS49587GEVKOS
AMIS49587
http://onsemi.com
19
FROM
MAINS
Clock & Control
M50Hz_IN
ZeroCross
PLL
CHIP_CLK
Debounce
Filter
3V3_A
1M
W
Figure 12. Zero Cross Detector with Falling Edge Debouncer
The zero crossing detector output is logic zero when the
input is lower than the falling threshold level and a logic one
when the input is higher than the rising threshold level. The
falling edges of the output of the zero crossing detector are
debounced by a period between 0.5 ms and 1 ms. The
Rising edges are not debounced.
t
10 ms
VMAINS
ZeroCross
tZCD
VIRM50HZIN
VIFM50HZIN
tDEBOUNCE = 0,5 .. 1 ms
Figure 13. Zero Cross Detector Signals and Timing (Example for 50 Hz)
6.1.2 50/60 Hz PLL
The output of the zero crossing detector is used as an input
for a PLL. The PLL generates the clock CHIP_CLK which
is 8 times the bit rate and which is in phase with the rising
edge crossings. The PLL locks on the zero crossing from
negative to positive phase. The bit rate is always an even
multiple of the mains frequency, so following combinations
are possible:
Table 22. CHIP_CLK IN FUNCTION OF SELECTED
BAUD RATE AND MAINS FREQUENCY
BAUD[1:0]
MAINS_FREQ
Baudrate
CHIP_CLK
00
50 Hz
300
2400 Hz
01
600
4800 Hz
10
1200
9600Hz
11
2400
19200 Hz
00
60 Hz
360
2880 Hz
01
720
5760 Hz
10
1440
11520Hz
11
2880
23040 Hz
In case no zero crossings are detected the PLL freezes its
internal timers in order to maintain the CHIP_CLK timing.
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