參數(shù)資料
型號(hào)： AMIS49587GEVK
廠(chǎng)商： ON Semiconductor
文件頁(yè)數(shù)： 3/55頁(yè)
文件大小： 0K
描述： KIT EVALUATION AMIS49587
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，電源線(xiàn)路收發(fā)器
嵌入式： 否
已用 IC / 零件： AMIS49587
已供物品： 2 個(gè)板，線(xiàn)纜，CD，文檔
其它名稱(chēng)： AMIS49587GEVKOS
AMIS49587
http://onsemi.com
11
4 ELECTRICAL CHARACTERISTICS
4.1
DC AND AC CHARACTERISTICS
4.1.1 Oscillator: Pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on the
static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 8. OSCILLATOR
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Crystal frequency
(Note 1)
fCLK
100 ppm
24
+100 ppm
MHz
Duty cycle with quartz connected
(Note 1)
40
61
%
Startup time
(Note 1)
Tstartup
50
ms
Maximum Capacitive load on XOUT
XIN used as clock input
CLXOUT
50
pF
Low input threshold voltage
XIN used as clock input
VILXOUT
0.3 VDD
V
High input threshold voltage
XIN used as clock input
VIHXOUT
0.7 VDD
V
Low output voltage
XIN used as clock input,
XOUT = 2 mA
VOLXOUT
0.3
V
High input voltage
XIN used as clock input
VOHXOUT
VDD0.3
V
1. Guaranteed by design. Maximum allowed series loss resistance up to 80 W.
4.1.2 Zero Crossing Detector and 50/60 Hz PLL: Pin M50HZ_IN
Table 9. ZERO CROSSING DETECTOR AND 50/60 Hz PLL
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Maximum peak input current
ImpM50HZIN
20
mA
Maximum average input current
During 1 ms
ImavgM50HZIN
2
mA
Mains voltage (ms) range
With protection resistor at
M50HZIN
VMAINS
90
550
V
Rising threshold level
(Note 2)
VIRM50HZIN
1.9
V
Falling threshold level
(Note 2)
VIFM50HZIN
0.82
V
Hysteresis
(Note 2)
VHY50HZIN
0.4
V
Lock range for 50 Hz (Note 3)
MAINS_FREQ = 0 (50 Hz)
Flock50Hz
45
55
Hz
Lock range for 60 Hz (Note 3)
MAINS_FREQ = 0 (60 Hz)
Flock60Hz
54
66
Hz
Lock time (Note 3)
MAINS_FREQ = 0 (50 Hz)
Tlock50Hz
15
s
Lock time (Note 3)
MAINS_FREQ = 0 (60 Hz)
Tlock60Hz
20
s
Frequency variation without going out of
lock (Note 3)
MAINS_FREQ = 0 (50 Hz)
DF60Hz
0.1
Hz/s
Frequency variation without going out of
lock (Note 3)
MAINS_FREQ = 0 (60 Hz)
DF50Hz
0.1
Hz/s
Jitter of CHIP_CLK (Note 3)
JitterCHIP_CLK
25
ms
2. Measured relative to VSS.
3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed
by the digital test patterns.
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