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參數(shù)資料
| 型號： | AMIS49587GEVK |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 9/55頁 |
| 文件大小： | 0K |
| 描述： | KIT EVALUATION AMIS49587 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，電源線路收發(fā)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AMIS49587 |
| 已供物品： | 2 個板，線纜，CD，文檔 |
| 其它名稱： | AMIS49587GEVKOS |
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AMIS49587
http://onsemi.com
17
the frame is correct, it is passed to the external
processor.
Test Mode:
The Test Mode is used to test the compliance of a
PLC modem conforms to CENELEC. EN 500651
by a Continuous broadcast of fS or fM.
5.2
FUNCTIONAL DESCRIPTION
The block diagram below represents the main functional
units of the AMIS49587:
Figure 9. SFSK Modem AMIS49587 Block Diagram
Communication Controller
ARM
Risc
Core
Serial
Comm.
Interface
Local Port
Test
Control
POR
Watchdog
Timer 1 & 2
Interrupt
Control
Data
RAM
Program
ROM
AAF
AGC
A/D
REF
SFSK
Demodulator
Receiver (S FSK Demodulator)
Clock and Control
Zero
crossing
PLL
OSC
Clock Generator
& Timer
Transmit Data
& Sine Synthesizer
D/A
LP
Filter
Transmitter (SFSK Modulator)
RX_DATA
RESB
JTAG I /F
TEST
TX_ENB
TX_OUT
ALC_IN
RX_OUT
RX_IN
REF_OUT
M50Hz_IN
XIN
XOUT
VDDA
VSSA
VDDD
VSSD
AMIS49587
PC20091019.2
TO Power Amplifier
FROM Line Coupler
TO Application
Micro Controller
TxD
RxD
T_REQ
BR0
BR1
CRC
TX_DATA / PRE _SLOT
5
5.2.1 Transmitter
The AMIS49587 Transmitter function block prepares
the communication signal which will be sent on the
transmitting channel during the transmitting phase. This
block is connected to a power amplifier which injects the
output signal on the mains through a linecoupler.
5.2.2 Receiver
The analog signal coming from the linecoupler is low
pass filtered in order to avoid aliasing during the conversion.
Then the level of the signal is automatically adapted by an
automatic gain control (AGC) block. This operation
maximizes the dynamic range of the incoming signal. The
signal is then converted to its digital representation using
sigma delta modulation. From then on, the processing of the
data is done in a digital way. By using dedicated hardware,
a direct quadrature demodulation is performed. The signal
demodulated in the base band is then low pass filtered to
reduce the noise and reject the image spectrum.
Clock and Control
According to the IEC6133451 standard, the frame
data is transmitted at the zero crossing of the mains voltage.
In order to recover the information at the zero crossing, a
zero crossing detection of the mains is performed. A
phaselocked loop (PLL) structure is used in order to allow
a more reliable reconstruction of the synchronization. This
PLL permits as well a safer implementation of the
”repetition with credit” function (also known as chorus
transmission). The clock generator makes use of a precise
quartz oscillator master. The clock signals are then obtained
by the use of a programmed division scheme. The support
circuits are also contained in this block. The support circuits
include the necessary blocks to supply the references
voltages for the AD and DA converters, the biasing currents
and power supply sense cells to generate the right power off
and startup conditions.
20 ms
24 bit @ 1200 baud
Figure 10. Data Stream is in Sync with Zero
Crossings of the Mains (Example for 50 Hz)
5.2.3 Communication Controller
The Communication Controller block includes the
microprocessor, its peripherals: RAM, ROM, UART,
TIMER, and the Power on reset. The processor uses the
ARM Reduced Instruction Set Computer (RISC)
architecture optimized for IO handling. For most of the
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