- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16183 > AMIS49587GEVK (ON Semiconductor)KIT EVALUATION AMIS49587 PDF資料下載
參數(shù)資料
| 型號： | AMIS49587GEVK |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 14/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVALUATION AMIS49587 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，電源線路收發(fā)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AMIS49587 |
| 已供物品： | 2 個板，線纜，CD，文檔 |
| 其它名稱： | AMIS49587GEVKOS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
AMIS49587
http://onsemi.com
21
6.1.4 Clock Generator and Timer
The CHIP_CLK and fCLK are used to generate a number
of timing signals used for the synchronization and interrupt
generation. The timing generation has a fixed repetition rate
which corresponds to the length of a physical subframe. (see
paragraph Send and Receive network data).
The timing generator is the same for transmit and receive
mode. When AMIS49587 switches from receive to
transmit and back from transmit to receive, the
R_CHIP_CNT counter value is maintained. As a result all
timing signals for receive and transmit have the same
relative timing. The following timing signals are defined as:
BIT_CLK
63
64
65
2871 2872
1
0
2879
2
3
4
5
6
7
8
9
CHIP_CLK
BYTE_CLK
FRAME_CLK
PRE_FRAME_CLK
PRE_BYTE_CLK
R_CHIP_CNT
PRE_SLOT
Start of the physical subframe
Figure 16. Timing Signals
CHIP_CLK is the output of the PLL and 8 times the bit rate on the physical interface. See also paragraph 50/60 Hz PLL
BIT_CLK is active at counter values 0,8,16, .. 2872 and inactive at all other counter values. This signal is used to indicate the
transmission of a new bit.
BYTE_CLK is active at counter values 0,64,128, .. 2816 and inactive at all other counter values. This signal is used to indicate
the transmission of a new byte.
FRAME_CLK is active at counter values 0 and inactive at all other counter values. This signal is used to indicate the
transmission or reception of a new frame.
PRE_BYTE_CLK is a signal which is 8 CHIP_CLK sooner than BYTE_CLK. This signal is used as an interrupt for the
internal microcontroller and indicates that a new byte for transmission must be generated.
PRE_FRAME_CLK is a signal which is 8 CHIP_CLK sooner than FRAME_CLK. This signal is used as an interrupt for the
internal microcontroller and indicates that a new frame will start at the next FRAME_CLK.
PRE_SLOT is logic 1 between the rising edge of PRE_FRAME_CLK and the rising edge of FRAME_CLK. This signal can
be provided at the digital output pin TX_DATA_PRE_SLOT when R_CONF[7] = 0 (See paragraph WriteConfigRequest, field
TX_DATA_PRESLOT_SEL) and can be used by the external host controller to synchronize its software with the
FRAME_CLK of AMIS49587.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-J51-EY-S | CONVERTER MOD DC/DC 12V 50W |
| 383LX473M025A062 | CAP ALUM 47000UF 25V 20% SNAP |
| M3DDK-3418R | IDC CABLE - MKR34K/MC34M/MKR34K |
| CMH322522-27NML | INDUCTOR WIREWOUND .027UH 1210 |
| VI-J50-EZ-F4 | CONVERTER MOD DC/DC 5V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMIS-50050 | 制造商:ON Semiconductor 功能描述:SPREAD SPECTRUM BASEBAND CNTRLR - Trays 制造商:ON Semiconductor 功能描述:SPREAD SPECTRUM BASEBAND CNTRLR - Tape and Reel |
| AMIS-50051 | 制造商:ON Semiconductor 功能描述:DMOD 32LQFP / - Trays 制造商:ON Semiconductor 功能描述:DMOD - Tape and Reel |
| AMIS-52000 | 制造商:AMI 制造商全稱:AMI 功能描述:Single-Chip Radio Transceiver |
| AMIS-52050 | 制造商:ON Semiconductor 功能描述:WIRELESS LOW POWER TRANSCEIVER - 433MHZ (300-700MHZ), SSOP - Rail/Tube 制造商:ON Semiconductor 功能描述:WIRELESS LOW POWER TRANSCEIVER - 433MHZ (300-700MHZ), SSOP - Tape and Reel |
| AMIS-52100 | 制造商:AMI 制造商全稱:AMI 功能描述:Transceiver with Clock and Data Recovery |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。