參數(shù)資料
型號: AT85C51SND3B1-RTTUL
廠商: Atmel
文件頁數(shù): 109/119頁
文件大小: 0K
描述: IC DECODER/ENCODER DGTL 100-LQFP
標(biāo)準(zhǔn)包裝: 90
類型: 音頻編碼器/解碼器
應(yīng)用: 移動電話,手機,視頻顯示器
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
9
AT85C51SND3B
7632D–MP3–01/07
Table 3. Timer 0 and Timer 1 Signal Description
P4.6:0
I/O
Port 4
P4 is a 7-bit bidirectional I/O port with internal pull-ups.
OCLK
DCLK
DDAT
DSEL
NFCE1/SMLCK
NFCE2/SMINS
NFCE3/SMCE
P5.3:0
I/O
Port 5
P5 is a 4-bit bidirectional I/O port with internal pull-ups.
LRD/LDE
SDR
LCS
SCS
LA0/LRS
SA0
LWR/LRW
SWR
Signal
Name
Type
Description
Alternate
Function
INT0
I
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set,
bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set
by a low level on INT0.
P3.2
RTS
SCK
INT1
I
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by
GATE1 bit in TCON register.
External Interrupt 1
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set,
bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set
by a low level on INT1.
P3.3
CTS
SS
T0
I
Timer 0 External Clock Input
When timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
P3.4
Signal
Name
Type
Description
Alternate
Function
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