參數(shù)資料
型號(hào): AT85C51SND3B1-RTTUL
廠商: Atmel
文件頁數(shù): 45/119頁
文件大小: 0K
描述: IC DECODER/ENCODER DGTL 100-LQFP
標(biāo)準(zhǔn)包裝: 90
類型: 音頻編碼器/解碼器
應(yīng)用: 移動(dòng)電話,手機(jī),視頻顯示器
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
31
AT85C51SND3B
7632D–MP3–01/07
Figure 19. System Clock Generator Block Diagram and Symbols
Table 26. System Clock Selection
X2 Feature
Unlike standard C51 products that require 12 clock periods per machine cycle, the
AT85C51SND3B needs only 6 clock periods per machine cycle. This feature called the
“X2 feature” can be enabled using the X2 bit(1) in CK CO N and al low s the
AT85C51SND3B to operate in 6 or 12 clock periods per machine cycle. As shown in
Figure 19, both CPU and peripheral clocks are affected by this feature. Figure 20 shows
the X2 mode switching waveforms. After reset the standard mode is activated. In stan-
dard mode the CPU and peripheral clock frequency is the oscillator frequency divided by
2 while in X2 mode, it is the oscillator frequency.
Figure 20. Mode Switching Waveforms
DFC/NFC Clock
Generator
In order to optimize the data transfer throughput between the DFC and the NFC, both
peripherals share the same clock frequency. The DFC and NFC clock generator block
diagram is shown in Figure 21 and is based on a frequency selector.
Frequency selection is done using DNFCKS2:0 bits in CKSEL (see Table 33) according
Frequency is enabled by setting DNFCKEN bit in CKEN.
SYSCKS1:0
Clock Selection (FSYS)
00
F
OSC (default)
01
24 MHz
10
30 MHz
11
40 MHz
IDL
PCON.0
X2
CKCON.0
SYSCKS1:0
CKSEL.1:0
CLOCK
GEN
24 MHz
30 MHz
40 MHz
FSYS
00
01
10
11
OSC
CLOCK
Peripheral
CPU Core
0
1
÷ 2
Clock
PER
CLOCK
Peripheral Clock Symbol
CPU
CLOCK
CPU Core Clock Symbol
AUD
CLOCK
Audio Clock Symbol
Audio Controller
Clock
FSYS ÷ 2
F
SYS
Clock
X2 bit
X2 Mode
STD Mode
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