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參數(shù)資料
| 型號： | AT85C51SND3B1-RTTUL |
| 廠商： | Atmel |
| 文件頁數(shù)： | 34/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DECODER/ENCODER DGTL 100-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 音頻編碼器/解碼器 |
| 應(yīng)用： | 移動電話，手機，視頻顯示器 |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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21
AT85C51SND3B
7632D–MP3–01/07
Battery Voltage Monitor
The battery voltage monitor is a 5-bit / 50 mV resolution A to D converter with fixed con-
version range as detailed in Table 18.
Table 18. Battery Voltage Value
Conversion Management
The battery voltage monitor is turned on by setting the VBPEN and VBCEN bits in
PCON (see Table 20). VBPEN bit is set first and VBCEN bit is set 1 ms later. An addi-
tional delay of 16 cycles is required before lauching any conversion.
Launching a conversion is done by setting VBEN bit in VBAT (see Table 22). VBEN is
automatically cleared at the end of the conversion which takes 34 clock periods. At this
step two cases occur:
Voltage is valid (inside conversion range)
VBERR is cleared and conversion value is set in VB4:0 according to Table 18.
Voltage is invalid (out of conversion range)
VBERR is set and value reported by VB4:0 is indeterminate.
Power Reduction Mode
Two power reduction modes are implemented in the AT85C51SND3B: the Idle mode
and the Power-down mode. These modes are detailed in the following sections. In addi-
tion to these power reduction modes, the clocks of the core and peripherals can be
dynamically divided by 2 using the X2 mode as detailed in Section “X2 Feature”,
page 31.
Lock Mode
In order to allow firmware to efficiently enter in idle mode and not to lose any events that
should come from one or more interrupts, power reduction modes entry are conditioned
to an hardware bit: PMLCK in PCON.
PMLCK is set by software in each ISR that needs to report an event to the system and
thus disables entry in power reduction mode and allows immediate processing of this
event. It is cleared by software after exiting power reduction mode.
As shown in Figure 9, when power reduction modes are disabled by setting PMLCK, IDL
and PD bits in PCON can not be set and idle or power down modes are not entered.
Figure 9. Power Reduction Controller Block Diagram
VB4:0
Battery Voltage (V)
00000
[0.9 - 0.95[
00001
[0.95 - 1.0[
00010
[1.0 - 1.05[
…
01110
[1.6 - 1.65[
01111
[1.65 - 1.7[
10000
[1.7 - 1.75[
System Idle
System Power Down
IDL
PCON.0
PD
PCON.1
PMLCK
PCON.2
Write to IDL
Write to PD
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| AT85C51SND3B2-RTTUL | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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| AT85C51SND4B1-7FTUL | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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