參數(shù)資料
型號(hào)： AT85C51SND3B1-RTTUL
廠商： Atmel
文件頁數(shù)： 94/119頁
文件大小： 0K
描述： IC DECODER/ENCODER DGTL 100-LQFP
標(biāo)準(zhǔn)包裝： 90
類型： 音頻編碼器/解碼器
應(yīng)用： 移動(dòng)電話，手機(jī)，視頻顯示器
電壓 - 電源，數(shù)字： 1.65 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
76
AT85C51SND3B
7632D–MP3–01/07
Operation
After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and
E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip
reset to disable it. If it is not cleared using the previous sequence, the WDT overflows
and forces a chip reset. This overflow generates a low level 96 oscillator periods pulse
on the RST pin to globally reset the application (refer to Section “Watchdog Timer
Reset”, page 25).
The WDT time-out period can be adjusted using WTO2:0 bits located in the WDTPRG
register accordingly to the formula shown in Figure 44. In this formula, WTOval repre-
sents the decimal value of WTO2:0 bits. Table 88 reports the time-out period depending
on the WDT frequency.
Figure 44. WDT Time-Out Formula
Notes:
1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1:
FWDT = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode when WTX2 = 0: FWDT = FOSC.
Behavior during Idle and
Power-down Modes
Operation of the WDT during power reduction modes deserves special attention.
The WDT continues to count while the CPU core is in Idle mode. This means that you
must dedicate some internal or external hardware to service the WDT during Idle mode.
One approach is to use a peripheral Timer to generate an interrupt request when the
Timer overflows. The interrupt service routine then clears the WDT, reloads the periph-
eral Timer for the next service period and puts the CPU core back into Idle mode.
The Power-down mode stops all phase clocks. This causes the WDT to stop counting
and to hold its count. The WDT resumes counting from where it left off if the Power-
down mode is terminated by INT0, INT1 or keyboard interrupt. To ensure that the WDT
does not overflow shortly after exiting the Power-down mode, it is recommended to clear
the WDT just before entering Power-down mode.
The WDT is cleared and disabled if the Power-down mode is terminated by a reset.
Table 88. WDT Time-Out Computation
WTO2 WTO1 WTO0
WDT
TO(ms) / FWDT
6 MHz(1)
8 MHz(1)
10 MHz(1)
12 MHz
16 MHz(2)
20 MHz(2)
24 MHz(2)
0
16.38
12.28
9.83
8.19
6.14
4.92
4.1
0
1
32.77
24.57
19.66
16.38
12.28
9.83
8.19
0
1
0
65.54
49.14
39.32
32.77
24.57
19.66
16.36
0
1
131.07
98.28
78.64
65.54
49.14
39.32
32.77
1
0
262.14
196.56
157.29
131.07
98.28
78.64
65.54
1
0
1
524.29
393.1
314.57
262.14
196.56
157.29
131.07
1
0
1049
786.24
629.15
524.29
393.12
314.57
262.14
1
2097
1572
1258
1049
786.24
629.15
524.29
WDT
TO=
F
WDT
6
(214 2WTOval)
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