參數(shù)資料
型號: AT85C51SND3B1-RTTUL
廠商: Atmel
文件頁數(shù): 48/119頁
文件大?。?/td> 0K
描述: IC DECODER/ENCODER DGTL 100-LQFP
標準包裝: 90
類型: 音頻編碼器/解碼器
應用: 移動電話,手機,視頻顯示器
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
34
AT85C51SND3B
7632D–MP3–01/07
Registers
Reset Value = 0000 0000b
Table 31. CKCON Register
CKCON (0.8Fh) – Clock Control Register
7
6
5
4
3
2
1
0
-
WDX2
OSCAMP
OSCF1
OSCF0
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is always 0. Do not set this bit.
6
WDX2
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2
independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
5
OSCAMP
Oscillator Amplifier Control Bit
Set to optimize power consumption by disabling the oscillator amplifier when an
external clock is used.
Clear to enable the oscillator amplifier in case of crystal usage (default).
4-3
OSCF1:0
Oscillator Frequency Range Bits
Set this bits according to Table 23 to optimize power consumption.
2
T1X2
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2
independent).
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
1
T0X2
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2
independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
0
X2
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER =
F
OSC/2).
Set to select 6 clock periods per machine cycle (X2 mode, F
CPU = FPER = FOSC).
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