- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1905 > ATMEGA103-6AI (Atmel)IC MCU 128K 6MHZ A/D IT 64TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ATMEGA103-6AI |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 24/141頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 128K 6MHZ A/D IT 64TQFP |
| 產(chǎn)品培訓(xùn)模塊： | megaAVR Introduction |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 6MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 128KB（64K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤 |
| 配用： | ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)當(dāng)前第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)
12
ATmega103(L)
0945I–AVR–02/07
The 4096 first Data memory locations address both the Register File, the I/O memory
and the internal Data SRAM. The first 96 locations address the Register File and I/O
memory, and the next 4000 locations address the internal Data SRAM.
An optional external Data SRAM can be used with the ATmega103(L). This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area
starts at the address following the internal SRAM. If a 64K external SRAM is used, 4K of
the external memory is lost as the addresses are occupied by internal memory.
When the addresses accessing the SRAM memory space exceeds the internal Data
memory locations, the external Data SRAM is accessed using the same instructions as
for the internal Data memory access. When the internal Data memories are accessed,
the read and write strobe pins (RD and WR) are inactive during the whole access cycle.
External SRAM operation is enabled by setting the SRE bit in the MCUCR Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, PUSH and
POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts,
subroutine calls and returns take two clock cycles extra because the 2-byte Program
Counter is pushed and popped. When external SRAM interface is used with wait state,
two additional clock cycles are used per byte. This has the following effect: Data transfer
instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns
will need four clock cycles more than specified in the “Instruction Set Summary” on page
The five different addressing modes for the Data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The Indirect with Displacement mode features 63 address locations reached from the
base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic Pre-decrement and Post-
increment, the address registers X, Y, and Z are decremented and incremented.
The entire Data address space including the 32 general purpose working registers and
the 64 I/O Registers are all accessible through all these addressing modes. See the
next section for a detailed description of the different addressing modes.
Program and Data
Addressing Modes
The ATmega103(L) AVR RISC microcontroller supports powerful and efficient address-
ing modes for access to the Program memory (Flash) and Data memory (SRAM,
Register File and I/O memory). This section describes the different addressing modes
supported by the AVR architecture. In the figures, OP means the operation code part of
the instruction word. To simplify, not all figures show the exact location of the address-
ing bits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATMEGA128A-AUR | MCU AVR 128K FLASH 16MHZ 64TQFP |
| ATMEGA128L-8MJ | IC MCU AVR 128K 8MHZ LV 64-QFN |
| ATMEGA16-16MUR | MCU AVR 16KB FLASH 16MHZ 44QFN |
| ATMEGA164PA-AN | IC MCU AVR 16K FLASH 44TQFP |
| ATMEGA164PA-CUR | MCU AVR 16KB FLASH 20MHZ 49VFBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATMEGA103L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 128K Bytes In-System Programmable Flash |
| ATMEGA103L-4AC | 功能描述:8位微控制器 -MCU TQFP-64 128K FLASH 3 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATMEGA103L-4AI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash |
| ATMEGA128 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 128K Bytes In-System Programmable Flash |
| ATMEGA128(L) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATmega128(L) Preliminary Summary [Updated 9/03. 23 Pages] |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。