參數(shù)資料
型號： ATMEGA103-6AI
廠商： Atmel
文件頁數(shù)： 88/141頁
文件大?。?/td> 0K
描述： IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 90
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 6MHz
連通性： SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
配用： ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
50
ATmega103(L)
0945I–AVR–02/07
Timer/Counter1 Control
Register B – TCCR1B
Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the Input Capture Trigger Noise Canceler function
is disabled. The Input Capture is triggered at the first rising/falling edge sampled on the
Input Capture pin PD4(IC1) as specified. When the ICNC1 bit is set (one), four succes-
sive samples are measured on PD4(IC1), and all samples must be high/low according to
the Input Capture trigger specification in the ICES1 bit. The actual sampling frequency is
XTAL clock frequency.
Bit 6 – ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the
Input Capture Register (ICR1) on the falling edge of the Input Capture pin – PD4(IC1).
While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the
Input Capture Register on the rising edge of the Input Capture pin – PD4(IC1).
Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock
cycle after a Compare A Match. If the CTC1 control bit is cleared, Timer/Counter1 con-
tinues counting and is unaffected by a compare match. Since the compare match is
detected in the CPU clock cycle following the match, this function will behave differently
when a prescaling higher than 1 is used for the Timer. When a prescaling of 1 is used
and the Compare A Register is set to C, the Timer will count as follows if CTC1 is set:
... | C-2 | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the Timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 | ...
In PWM mode, this bit has no effect.
0
1
Timer/Counter1 is an 8-bit PWM.
1
0
Timer/Counter1 is a 9-bit PWM.
1
Timer/Counter1 is a 10-bit PWM.
Table 16. PWM Mode Select
PWM11
PWM10
Description
Bit
7
6
5
4
3
2
1
0
$2E ($4E)
ICNC1
ICES1
–
CTC1
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
Initial Value
0
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