參數(shù)資料
型號(hào): ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 71/141頁
文件大?。?/td> 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
35
ATmega103(L)
0945I–AVR–02/07
Timer/Counter Interrupt Flag
Register – TIFR
Bit 7 – OCF2: Output Compare Flag 2:
The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and
the data in OCR2 – Output Compare Register 2. OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2
Compare Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2 Output
Compare interrupt is executed.
Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, and TOIE2
(T im er/Co u n t er1 Ove r flow Inte rrup t En able) an d TO V2 a r e set (o ne) , th e
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 advances from $00.
Bit 5 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an Input Capture event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit,
TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture interrupt is executed.
Bit 4 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Interrupt Enable) and the OCF1A are set (one), the
Timer/Counter1 Compare A Match interrupt is executed.
Bit 3 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1B – Output Compare Register 1B. OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare Match Interrupt Enable) and the OCF1B are set (one), the
Timer/Counter1 Compare B Match interrupt is executed.
Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1
Bit
7
6
5
4
3
2
1
0
$36 ($56)
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0
TIFR
Read/Write
R/W
Initial Value
0
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