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參數(shù)資料
| 型號： | BSP255 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | P-channel enhancement mode vertical D-MOS transistor |
| 中文描述： | 0.325 A, 300 V, 17 ohm, P-CHANNEL, Si, POWER, MOSFET |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 65K |
| 代理商： | BSP255 |
1996 Aug 05
5
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSP255
CHARACTERISTICS
T
j
= 25
°
C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
300
0.8
TYP.
45
15
3
2.3
MAX.
2
100
±
100
17
20
25
UNIT
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
gate leakage current
drain-source on-state resistance
V
GS
= 0; I
D
=
10
μ
A
V
GS
= V
DS
; I
D
=
1 mA
V
GS
= 0; V
DS
=
240 V
V
GS
=
±
20 V; V
DS
= 0
V
GS
=
10 V; I
D
=
160 mA
V
GS
=
4.5 V; I
D
=
80 mA
V
GS
=
2.8 V; I
D
=
50 mA
V
GS
= 0; V
DS
=
50 V; f = 1 MHz
V
GS
= 0; V
DS
=
50 V; f = 1 MHz
V
GS
= 0; V
DS
=
50 V; f = 1 MHz
V
GS
=
10 V; V
DD
=
50 V;
I
D
=
160 mA; T
amb
= 25
°
C
V
GS
=
10 V; V
DD
=
50 V;
I
D
=
160 mA; T
amb
= 25
°
C
V
GS
=
10 V; V
DD
=
50 V;
I
D
=
160 mA; T
amb
= 25
°
C
V
V
nA
nA
pF
pF
pF
nC
C
iss
C
oss
C
rss
Q
g
input capacitance
output capacitance
reverse transfer capacitance
total gate charge
Q
gs
gate-source charge
0.1
nC
Q
gd
gate-drain charge
0.7
nC
Switching times
(see Fig.11)
t
d(on)
t
r
t
on
t
d(off)
t
f
t
off
turn-on delay time
rise time
turn-on switching time
turn-off delay time
fall time
turn-off switching time
V
GS
= 0 to
10 V; V
DD
=
50 V;
I
D
=
160 mA; R
gen
= 50
2.4
1.6
4
13
12
25
ns
ns
ns
ns
ns
ns
V
GS
=
10 to 0 V; V
DD
=
50 V;
I
D
=
160 mA; R
gen
= 50
Source-drain diode
V
SD
source-drain forward voltage
V
GD
= 0; I
S
=
0.5 A
1.8
V
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