參數(shù)資料
型號(hào)： BU-62864
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？
文件頁(yè)數(shù)： 10/56頁(yè)
文件大?。?/td> 368K
代理商： BU-62864
10
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
BITS 15-0 ARE RESERVED
Write these bits as 0s.
BITS 31-2 ARE RESERVED
Must be written as. 0s.
CLEAR FAIL-SAFE INTERRUPT
Clears the Fail-safe Interrupt when set to "1". Fail-safe interrupts
can also be cleared via the Fail-safe Interrupt Autoclear mecha-
nism, enabled by bit 18 in Reg 1.
ACE RESET
Resets the ACE when set to "1".
PCI ENHANCED MINI-ACE REGISTER AND MEMORY
ADDRESSING
The software interface of the Enhanced Mini-ACE portion of the
PCI EMA to the host processor consists of 24 internal opera-
tional registers for normal operation, an additional 24 test regis-
ters, plus 64K words of shared memory address space.The PCI
Enhanced Mini-ACE's 4K X 16 or 64K X 17 internal RAM resides
in this address space.
31 (MSB)
RESERVED - BIT 31 (MSB)
TABLE 16. REG6 GENERAL PURPOSE REGISTER
(READ/WRITE 818H)
BIT
DESCRIPTION
0 (LSB)
RESERVED - BIT 0 (LSB)
31 (MSB)
RESERVED, WRITE AS 0 - BIT 31 (MSB)
TABLE 17. REG7 RESERVED REGISTER
(WRITE 81CH)
BIT
DESCRIPTION
1
CLEAR FAILSAFE INTERRUPT
0 (LSB)
ACE RESET - BIT 0 (LSB)
This register will be all 0s after RST#. No access to this regis-
ter is needed for normal applications.
For normal operation, the host processor only needs to access
the lower 32 register address locations (00-1Fh, PCI BAR1 off-
set 00-7Ch).The next 32 locations (20-3F, PCI BAR1 offset 80h-
FCh) should be reserved, since many of these are used for fac-
tory test.
INTERNAL 1553 REGISTERS
The internal address mapping for the PCI Enhanced Mini-ACE
registers is illustrated in TABLE 18. Note that the address lines
shown are the PCI Enhanced Mini-ACE’s internal ACE register
bus and are left shifted 2 bits with respect to the PCI address: A0
= PCI A2, A1 = PCI A3, etc. For example, Interrupt mask regis-
ter #1 is located at PCI address BAR1 offset + 0h, Configuration
Register #1 is at BAR1 offset + 4h, etc.Note that TABLE 18 does
not show the internal A5 register address line, which is normally
0 and is set only for access to the reserved factory test registers.
The configuration registers will be cleared to 0000h after hard-
ware or software reset, with the exception of the Enhanced CPU
Access bit (bit 14 in Configuration register #6).
This register will be all 0s after RST#. This read/write register
is available for customer use, perhaps as a flag register for sig-
naling between bus masters.
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