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參數(shù)資料
| 型號： | BU-62864 |
| 英文描述： | MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| 中文描述： | 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？ |
| 文件頁數(shù)： | 21/56頁 |
| 文件大?。?/td> | 368K |
| 代理商： | BU-62864 |
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21
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
BC TIME REMAINING TO NEXT MESSAGE REGISTER
The BC Time Remaining to Next Message Register provides a
read-only indication of the time remaining before the start of the
next message in a BC frame. In the enhanced BC mode, this
timer may also be used for the BC message sequence control
processor's Delay (DLY) instruction, or for minor or major frame
control.The resolution of this register is 1 μs/LSB.
BC FRAME TIME/RT LAST COMMAND/MT TRIGGER
WORD REGISTER
In BC mode, this register is used to program the BC frame time,
for use in the frame auto-repeat mode.The resolution of this reg-
ister is 100 μs/LSB, with a range up to 6.55 seconds. In RT
mode, this register stores the current (or most previous) 1553
Command Word processed by the PCI Enhanced Mini-ACE RT.
In the Word Monitor mode, this register is used to specify a 16-
bit Trigger (Command) Word. The Trigger Word may be used to
start or stop the monitor, or to generate interrupts.
BC INITIAL INSTRUCTION LIST POINTER REGISTER
The BC Initial Instruction List Pointer Register enables the host
to assign the starting address for the enhanced BC Instruction
List.
RT STATUS WORD REGISTER AND BIT WORD
REGISTERS
The RT Status Word Register and BIT Word Registers provide
read-only indications of the RT Status and BIT Words.
TEST MODE REGISTERS 0-7
These registers are included for factory test. In normal operation,
these registers do not need to be accessed by the host processor.
CONFIGURATION REGISTERS #6 AND #7
Configuration Registers #6 and #7 are used to enable the PCI
Enhanced Mini-ACE features that extend beyond the architec-
ture of the ACE/Mini-ACE (Plus). These include the Enhanced
BC mode; Enhanced CPU Access (note that this bit is the only
configuration bit that is SET after reset), RT Global Circular
Buffer (including buffer size); the RT/MT Interrupt Status Queue,
including valid/invalid message filtering; enabling a software-
assigned RT address; clock frequency selection; a base address
for the "non-data" portion of PCI Enhanced Mini-ACE memory;
LSB filtering for the Synchronize (with data) time tag operations;
and enabling a watchdog timer for the Enhanced BC message
sequence control engine.
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
Users Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
BC CONDITION CODE REGISTER
The BC Condition Code Register is used to enable the host
processor to read the current value of the Enhanced BC
Message Sequence Control Engine's condition flags.
BC GENERAL PURPOSE FLAG REGISTER
The BC General Purpose Flag Register allows the host proces-
sor to be able to set, clear, or toggle any of the Enhanced BC
Message Sequence Control Engine's General Purpose condition
flags.
BIT TEST STATUS REGISTER
The BIT Test Status Register is used to provide read-only access
of the status of the RAM built-in self-tests (BIT).
BC GENERAL PURPOSE QUEUE POINTER
The BC General Purpose Queue Pointer provides a means for
initializing the pointer for the General Purpose Queue, for the
Enhanced BC mode. In addition, this register enables the host to
determine the current location of the General Purpose Queue
pointer, which is incremented internally by the Enhanced BC
message sequence control engine.
RT/MT INTERRUPT STATUS QUEUE POINTER
REGISTER
The RT/MT Interrupt Status Queue Pointer Register provides a
means for initializing the pointer for the Interrupt Status Queue,
for RT, MT, and RT/MT modes. In addition, this register enables
the host to determine the current location of the Interrupt Status
Queue pointer, which is incremented internally by the RT/MT
message processor.
BUS CONTROLLER (BC) ARCHITECTURE
The BC functionality for the PCI Enhanced Mini-ACE includes
two separate architectures: (1) the older, non-Enhanced mode,
which provides complete compatibility with the previous ACE and
Mini-ACE (Plus) generation products; and (2) the newer,
Enhanced BC mode.The Enhanced BC mode offers several new
powerful architectural features. These include the incorporation
of a highly autonomous BC message sequence control engine,
which greatly serves to offload the operation of the host CPU.
The Enhanced BC's message sequence control engine provides
a high degree of flexibility for implementing major and minor
frame scheduling; capabilities for inserting asynchronous mes-
sages in the middle of a frame; to separate 1553 message data
from control/status data for the purpose of implementing double
buffering and performing bulk data transfers; for implementing
message retry schemes, including the capability for automatic
bus channel switchover for failed messages; and for reporting
various conditions to the host processor by means of 4 user-
defined interrupts and a general purpose queue.
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