參數(shù)資料
型號： BU-62864
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？
文件頁數(shù)： 47/56頁
文件大?。?/td> 368K
代理商： BU-62864
47
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
+5V Vcc CH A
72
Channel A transceiver power.
72
+5V Vcc CH B
20
Channel B transceiver power.
20
+3.3V Logic
37
Logic power. For BU-62864/62843/62743, this pin must be connected to
+3.3V
.
For BU-62864 this pin must be connected to +5V.
37
Ground
17
Ground.
17
+5V RAM
26
—
TABLE 66. POWER AND GROUND
SIGNAL NAME
DESCRIPTION
PIN
BU-62843/62743
(4K RAM)
BU-62864
(64K RAM)
TX/RX_A (I/O)
5
Analog Transmit/Receive Inputs/Outputs. Connect directly to 1553 isolation
transformers.
TX/RX_A (I/O)
7
TX/RX_B (I/O)
13
TX/RX_B (I/O)
16
TABLE 67. 1553 ISOLATION TRANSFORMER INTERFACE (4)
SIGNAL NAME
DESCRIPTION
PIN (F & G PACKAGE)
SSFLAG (I) /
EXT_TRIG(I)
14
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input. In RT mode, if this
input is asserted low, the Subsystem Flag bit will be set in the PCI ENHANCED Mini-
ACE's RT Status Word. If the SSFLAG input is logic "0" while bit 8 of Configuration
Register #1 has been programmed to logic "1" (cleared), the Subsystem Flag RT
Status Word bit will become logic "1," but bit 8 of Configuration Register #1, SUBSYS-
TEM FLAG, will return logic "1" when read.That is, the sense on the SSFLAG input
has no effect on the SUBSYSTEM FLAG register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC
mode, if the external BC Start option is enabled (bit 7 of Configuration Register #1), a
low to high transition on this input will issue a BC Start command, starting execution of
the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG)
instruction, the PCI Enhanced Mini-ACE BC will wait for a low-to-high transition on
EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration
Register #1), a low to high transition on this input will initiate a monitor start. (RT the
monitor on low).
This input has no effect in Message Monitor mode.
TABLE 68. PROCESSOR INTERFACE CONTROL
SIGNAL NAME
DESCRIPTION
PIN (F & G PACKAGE)
18
18
19
19
65
65
67
67
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