參數(shù)資料
型號(hào)： BU-62864
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？
文件頁(yè)數(shù)： 48/56頁(yè)
文件大?。?/td> 368K
代理商： BU-62864
48
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
RTAD4 (MSB) (I)
8
RT Address inputs. If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is
programmed to logic "0" (default), then the PCI Enhanced Mini-ACE's RT address is
provided by means of these 5 input signals. In addition, if RT ADDRESS SOURCE is
logic "0", the source of RT address parity is RTADP.
There are many methods for using these input signals for designating the PCI
Enhanced Mini-ACE's RT address. For details, refer to the description of RT_AD_LAT.
If RT ADDRESS SOURCE is programmed to logic "1", then the PCI Enhanced Mini-
ACE's source for its RT address and parity is under software control, via data lines D5-
D0. In this case, the RTAD4-RTAD0 and RTADP signals are not used.
RTAD3 (I)
6
RTAD2 (I)
4
RTAD1 (I)
3
RTAD0 (LSB) (I)
1
RT_AD_LAT (I)
11
RT Address Latch.Input signal used to control the PCI Enhanced Mini-ACE's internal RT
address latch.If RT_AD_LAT is connected to logic "0", then the PCI Enhanced Mini-ACE RT
is configured to accept a hardwired (transparent) RT address from RTAD4-RTAD and RTADP
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on
RTAD4-RTAD0 and RTADP will be latched internally on the rising edge of RT_AD_LAT.
If RT_AD_LAT is connected to logic "1", then the PCI Enhanced Mini-ACE's RT address is
latchable under host processor control.In this case, there are two possibilities: (1) If bit 5 of
Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default),
then the source of the RT Address is the RTAD4-RTAD0 and RTADP input signals; (2) If RT
ADDRESS SOURCE is programmed to logic "1", then the source of the RT Address is the
lower 6 bits of the processor data bus, D5-D1 (for RTAD4-0) and D0 (for RTADP).
In
either
of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT
address to be latched by:(1) writing bit 15 of Configuration Register #3, ENHANCED MODE,
to logic "1";(2) writing bit 3 of Configuration Register #4, LATCH RT ADDRESS WITH CON-
FIGURATION REGISTER #5, to logic "1";and (3) writing to Configuration Register #5.In the
case of RT ADDRESS SOURCE = "1", then the values of RT address and RT address parity
must be written to the lower 6 bits of Configuration Register #5, via D5-D0.In the case where
RT ADDRESS SOURCE = "0", the bit values presented on D5-D0 become "don't care" .
RTADP
10
Remote Terminal Address Parity.This input signal must provide an odd parity sum with
RTAD4-RTAD0 in order for the RT to respond to non-broadcast commands.That is,
there must be an
odd
number of logic "1"s from among RTAD-4-RTAD0 and RTADP.
TABLE 69. RT ADDRESS
SIGNAL NAME
DESCRIPTION
PIN (F & G PACKAGE)
INCMD (O) /
MCRST (O)
12
In-command or Mode Code Reset.The function of this pin is controlled by bit 0 of
Configuration Register #7, MODE CODE RESET/INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or
Selective Message Monitor modes, INCMD is asserted low whenever a message is
being processed by the PCI Enhanced Mini-ACE. In Word Monitor mode, INCMD will
be asserted low for as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1",
MCRST will be active. In this case, MCRST will be asserted low for two clock cycles
following receipt of a Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this sig-
nal is inoperative; i.e., in this case, it will always output a value of logic "1".
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
Transmitter inhibit input for the Channel A and Channel B MIL-STD-1553 transmitters.
For normal operation, this input should be connected to logic "0".To force a shutdown of
Channel A and Channel B, a value of logic "1" should be applied to the TX_INH input.
Master Clear. Negative true Reset input, normally asserted low following power turn-on.
When coming out of a “reset” condition, please note that the rise time of MSTCLR must
be less than 10μs.
12
CLOCK_IN (I)
9
9
TX_INH_A/B (I)
15
15
MSTCLR(I)
2
2
TABLE 70. MISCELLANEOUS
SIGNAL NAME
DESCRIPTION
PIN (F & G PACKAGE)
BU-62843/62743
(4K RAM)
BU-62864
(64K RAM)
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