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參數(shù)資料
| 型號： | BU-62864 |
| 英文描述： | MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| 中文描述： | 符合MIL - STD - 1553器件|的PCI增強迷你ACE論壇？ |
| 文件頁數(shù)： | 6/56頁 |
| 文件大小： | 368K |
| 代理商： | BU-62864 |
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6
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
Memory Read Line commands will be accepted and treated as
Memory Read commands. Similarly, the PCI Enhanced Mini-
ACE will accept a memory Write and Invalidate command and
treat it as a Memory Write command.
ACE memory is accessed internally in 16-bit words, but memory
is accessed sequentially allowing for 32-bits of data to be read
from the PCI bus. In other words, if a 32-bit PCI read is request-
ed the first 16 bits of data would be read from the requested
internal address, the next 16 bits of data would be read from the
initial internal address + 1, and then the resulting 32-bit double
word would be transferred to the PCI bus. The PCI Enhanced
Mini-ACE supports 32-bit and 16-bit read and write operations, 8
bit reads will return 16 bit data, and 8 bit writes are illegal and will
cause target-aborts.
The ACE register mapping is located in PCI memory space.
Although the PCI Enhanced Mini-ACE can be accessed in 32-bit
words, all ACE registers are accessed in 16 bit word reads /
writes. If a 32-bit read is performed from the PCI bus in ACE reg-
ister space only the first 16 bits of data are valid.
This data sheet describes the PCI registers that are specific to
configuring the integrated terminal and shared RAM. For
specifics or definitions on other PCI bus configuration registers,
please see the PCI Local Bus specification revision 2.2.
VENDOR ID
The Vendor ID field contains the vendor's ID configuration regis-
ter. Data Device Corporation's ID code is 4DDCh.
DEVICE ID
The Device ID field is used to indicate the device being used.
This field is configured by DDC to reflect the part value of the
device. TABLE 4 represents all possible combinations for the
Device ID field.
RESERVED
These bits are read-only and return zeroes when read.
SERR# ENABLE
This is an enable bit for the SERR# driver. A value of 0b disables
the driver. A value of 1b enables the driver.The value after RST#
is 0b.
PARITY ERROR CONTROL
This bit controls the device's response to parity errors.When the
bit is 1b, the device will take its normal action when a parity error
is detected. When this bit is 0b, the device will ignore any parity
errors that it detects and continue normal operation. The value
after RST# is 0b.
Memory Read
0110 (6h)
Memory Write
0111 (7h)
Configuration Read
1010 (Ah)
Configuration Write
1011 (Bh)
TABLE 2. PCI TARGET COMMAND CODES
COMMAND TYPE
CODE (C/BE[3:0]#)
Memory Read Multiple
1100 (Ch)
Memory Read Line
1110 (Eh)
Memory Write and Invalidate
1111 (Fh)
TABLE 3. CONFIGURATION REGISTER SPACE FOR THE PCI ENHANCED MINI-ACE
ADDRESS
31
24
23
16
15
8
00h
Vendor ID
Device ID
7
0
04h
Command Register
Status Register
08h
Class Code = 078000 h
Header Type
00h
Base Address Register 0 (for ACE memory)
R/W and 0’s
see text
Base Address Register 1 (for ACE Registers)
Rev ID = 02h
Cache Line Size
00h
0Ch
Latency Timer
00h
BIST
00h
0Xh
(X varies with part #, see text)
04h
DDC Manufacturer Device ID value
(4DDCH)
10h
R/W
00h
00h
14h
R/W
R/W
R/W and 0’s
see text
00h
18h - 24h
Base Address Registers 2 through 5 (not Used) 00000000h
28h
Card Bus CIS pointer (Not Used) 00000000h
2Ch
Subsystem Device and Subsystem Vendor ID. Same as Configuration Register 0, Alias Reads to Configuration Register 00
30h
Expansion ROM Base Address (Not Used, bit 0 = 0)
34h - 38h
Reserved
3Ch
Max Lat.
00h
Min Gnt
00h
Interrupt Pin
01h
Interrupt Line
R/W
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