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參數(shù)資料
| 型號(hào)： | BU-62864 |
| 英文描述： | MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| 中文描述： | 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？ |
| 文件頁(yè)數(shù)： | 15/56頁(yè) |
| 文件大小： | 368K |
| 代理商： | BU-62864 |
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15
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
BC FRAME TIME REMAINING 0
0(LSB)
BC FRAME TIME REMAINING 15
15(MSB)
DESCRIPTION
BIT
TABLE 32. BC FRAME TIME REMAINING REGISTER
(READ/WRITE 0BH, PCI 2CH)
Note:
resolution = 100
μ
s per LSB
BC MESSAGE TIME REMAINING 0
0(LSB)
BC MESSAGE TIME REMAINING 15
15(MSB)
DESCRIPTION
BIT
TABLE 33. BC MESSAGE TIME REMAINING
REGISTER (READ 0CH, PCI 30H)
Note:
resolution = 1
μ
s per LSB
BIT 0
0(LSB)
BIT 15
15(MSB)
DESCRIPTION
BIT
TABLE 34. BC FRAME TIME / RT LAST COMMAND /
MT TRIGGER REGISTER (READ/WRITE 0DH, PCI 34H)
TABLE 35. RT STATUS WORD REGISTER
(READ 0EH, PCI 38H)
DESCRIPTION
11
BIT
15(MSB) LOGIC “0”
12
LOGIC “0”
14
LOGIC “0”
13
LOGIC “0”
10
MESSAGE ERROR
9
INSTRUMENTATION
8
SERVICE REQUEST
7
RESERVED
6
RESERVED
5
RESERVED
4
BROADCAST COMMAND RECEIVED
3
BUSY
LOGIC “0”
2
SSFLAG
1
DYNAMIC BUS CONTROL ACCEPT
0(LSB)
TERMINAL FLAG
COMMAND WORD CONTENTS ERROR
0(LSB)
RT-to-RT 2ND COMMAND WORD ERROR
1
RT-to-RT NO RESPONSE ERROR
2
TRANSMITTER SHUTDOWN B
RT-to-RT GAP / SYNC / ADDRESS ERROR
3
PARITY / MANCHESTER ERROR RECEIVED
4
INCORRECT SYNC RECEIVED
5
LOW WORD COUNT
6
HIGH WORD COUNT
7
BIT TEST FAIL
8
TERMINAL FLAG INHIBITED
9
TRANSMITTER SHUTDOWN A
10
HANDSHAKE FAILURE
12
LOOP TEST FAILURE A
13
LOOP TEST FAILURE B
14
TRANSMITTER TIMEOUT
15(MSB)
DESCRIPTION
BIT
11
TABLE 36. RT BIT WORD REGISTER
(READ 0FH, PCI 3CH)
CLOCK SELECT 0
0(LSB)
CLOCK SELECT 1
1
64-WORD REGISTER SPACE
2
GLOBAL CIRCULAR BUFFER SIZE 2
RESERVED
3
ENHANCED MESSAGE MONITOR
4
RT ADDRESS SOURCE
5
INTERRUPT STATUS QUEUE ENABLE
6
DISABLE VALID MESSAGES TO INTERRUPT STATUS
QUEUE
7
DISABLE INVALID MESSAGES TO INTERRUPT STATUS
QUEUE
8
GLOBAL CIRCULAR BUFFER SIZE 0
9
GLOBAL CIRCULAR BUFFER SIZE 1
10
GLOBAL CIRCULAR BUFFER ENABLE
12
COMMAND STACK POINTER INCREMENT ON EOM
(RT, MT)
13
ENHANCED CPU ACCESS
14
ENHANCED BUS CONTROLLER
15(MSB)
DESCRIPTION
BIT
11
TABLE 37. CONFIGURATION REGISTER #6
(READ/WRITE 18H, PCI 60H)
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