參數(shù)資料
型號(hào)： BU-62864
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？
文件頁(yè)數(shù)： 33/56頁(yè)
文件大小： 368K
代理商： BU-62864
33
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
host processor when the circular buffer is half full. At that time,
the host may proceed to read the received data words in the
upper half of the buffer, while the PCI Enhanced Mini-ACE RT
writes received data words to the lower half of the circular buffer.
Later, when the RT issues a 100% circular buffer rollover inter-
rupt, the host can proceed to read the received data from the
lower half of the buffer, while the PCI Enhanced Mini-ACE RT
continues to write received data words to the upper half of the
buffer.
INTERRUPT STATUS QUEUE
The PCI Enhanced Mini-ACE RT, Monitor, and combined
RT/Monitor modes include the capability for generating an inter-
rupt status queue. As illustrated in FIGURE 9, this provides a
chronological history of interrupt generating events and condi-
tions. In addition to the Interrupt Mask Register, the Interrupt
Status Queue provides additional filtering capability, such that
only valid messages and/or only invalid messages may result in
the creation of an entry to the Interrupt Status Queue. Queue
entries for invalid and/or valid messages may be individually dis-
abled by means of bits 8 and 7 of Configuration Register #6.
The pointer to the Interrupt Status Queue is stored in the INTER-
RUPT VECTOR QUEUE POINTER REGISTER (register
address 1F). This register must be initialized by the host, and is
subsequently incremented by the RT message processor. The
interrupt status queue is 64 words deep, providing the capability
to store entries for up to 32 messages.
The queue rolls over at addresses of modulo 64.The events that
result in queue entries include both message-related and non-
message related events. Note that the Interrupt Vector Queue
Pointer Register will always point to the next location (modulo 64)
following the last vector/pointer pair written by the PCI Enhanced
Mini-ACE RT, Monitor, or RT/Monitor.
Each event that causes an interrupt results in a two-word entry
to be written to the queue.The first word of the entry is the inter-
rupt vector. The vector indicates which interrupt event(s)/condi-
tion(s) caused the interrupt.
The interrupt events are classified into two categories: message
interrupt events and non-message interrupt events. Message-
based interrupt events include End-of-Message, Selected mode
code, Format error, Subaddress control word interrupt, RT
Circular buffer Rollover, Handshake failure, RT Command stack
rollover, transmitter timeout, MT data stack rollover, MT com-
mand stack rollover, RT Command stack 50% rollover, MT data
stack 50% rollover, MT command stack 50% rollover, and RT
Circular buffer 50% rollover. Non-message interrupt events/con-
ditions include time tag rollover, RT address parity error, RAM
parity error, and BIT completed.
Bit 0 of the interrupt vector (interrupt status) word indicates
whether the entry is for a message interrupt event (if bit 0 is logic
"1") or a non-message interrupt event (if bit 0 is logic "0").It is not
possible for one entry on the queue to indicate both a message
interrupt and a non-message interrupt.
As illustrated in FIGURE 9, for a message interrupt event, the
parameter word is a pointer. The pointer will reference the first
word of the RT or MT command stack descriptor (i.e., the Block
Status Word).
INTERRUPT
VECTOR
DATA WORD
BLOCK
DESCRIPTOR
STACK
PARAMETER
(POINTER)
INTERRUPT STATUS QUEUE
(64 Locations)
INTERRUPT VECTOR
QUEUE POINTER
REGISTER (IF)
BLOCK STATUS WORD
TIME TAG
DATA BLOCK POINTER
RECEIVED COMMAND
NEXT
VECTOR
FIGURE 9. RT (AND MONITOR) INTERRUPT STATUS QUEUE (SHOWN FOR MESSAGE INTERRUPT EVENT)
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