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參數(shù)資料
| 型號(hào)： | BU-62864 |
| 英文描述： | MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| 中文描述： | 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？ |
| 文件頁數(shù)： | 22/56頁 |
| 文件大?。?/td> | 368K |
| 代理商： | BU-62864 |
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22
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
In both the non-Enhanced and Enhanced BC modes, the PCI
Enhanced Mini-ACE BC implements all MIL-STD-1553B mes-
sage formats. Message format is programmable on a message-
by-message basis by means of the BC Control Word and the T/R
bit of the Command Word for the respective message. The BC
Control Word allows 1553 message format, 1553A/B type RT,
bus channel, self-test, and Status Word masking to be specified
on an individual message basis. In addition, automatic retries
and/or interrupt requests may be enabled or disabled for individ-
ual messages. The BC performs all error checking required by
MIL-STD-1553B.This includes validation of response time, sync
type and sync encoding, Manchester II encoding, parity, bit
count, word count, Status Word RT Address field, and various
RT-to-RT transfer errors. The PCI Enhanced Mini-ACE BC
response timeout value is programmable with choices of 18, 22,
50, and 130 μs. The longer response timeout values allow for
operation over long buses and/or use of the repeaters.
In its non-Enhanced mode, the PCI Enhanced Mini-ACE may be
programmed to process BC frames of up to 512 messages with
no processor intervention.In the Enhanced BC mode, there is no
explicit limit to the number of messages that may be processed
in a frame. In both modes, it is possible to program for either sin-
gle frame or frame auto-repeat operation. In the auto-repeat
mode, the frame repetition rate may be controlled either inter-
nally, using a programmable BC frame timer, or from an external
trigger input.
ENHANCED BC MODE: MESSAGE SEQUENCE
CONTROL
One of the major new architectural features of the PCI Enhanced
Mini-ACE series is its advanced capability for BC message
sequence control. The PCI Enhanced Mini-ACE supports highly
autonomous BC operation, which greatly offloads the operation
of the host processor.
The operation of the PCI Enhanced Mini-ACE's message
sequence control engine is illustrated in FIGURE 2.The BC mes-
sage sequence control involves an instruction list pointer regis-
ter; an instruction list which contains multiple 2-word entries; a
message control/status stack, which contains multiple 8-word or
10-word descriptors; and data blocks for individual messages.
The initial value of the instruction list pointer register is initialized
by the host processor (via Register 0D), and is incremented by
the BC message sequence processor (host readable via
Register 03). During operation, the message sequence control
processor fetches the operation referenced by the instruction list
pointer register from the instruction list.
Note that the pointer parameter referencing the first word of a
message's control/status block (the BC Control Word) must con-
tain an address value that is
modulo 8
. Also, note that if the
message is an RT-to-RT transfer, the pointer parameter must
contain an address value that is
modulo 16
.
OP CODES
The instruction list pointer register references a pair of words in
the BC instruction list: an op code word, followed by a parameter
word.The format of the op code word, which is illustrated in FIG-
URE 3, includes a 5-bit op code field and a 5-bit condition code
field.The op code identifies the instruction to be executed by the
BC message sequence controller.
Most of the operations are conditional, with execution dependent
on the contents of the condition code field. Bits 3-0 of the condi-
tion code field identify the particular condition. Bit 4 of the condi-
tion code field identifies the logic sense ("1" or "0") of the select-
ed condition code on which the conditional execution is depend-
ent. TABLE 52 lists all the op codes, along with their respective
OP CODE
P(POINTER)
DATA BLOCK
MESSAGE
CONTROL/STATUS
BLOCK
BC INSTRUCTION
LIST
BC INSTRUCTION
LIST POINTER REGISTER
BC CONTROL
WORD
COMMAND WORD
(Rx Command for
RT-to-RT transfer)
DATA BLOCK POINTER
TIME-TO-NEXT MESSAGE
TIME TAG WORD
BLOCK STATUS WORD
LOOPBACK WORD
RT STATUS WORD
2nd (Tx) COMMAND WORD
(for RT-to-RT transfer)
2nd RT STATUS WORD
(for RT-to-RT transfer)
INITIALIZE BY REGISTER
0D (RD/WR); READ CURRENT
VALUE VIA REGISTER 03
(RD ONLY)
FIGURE 2. BC MESSAGE SEQUENCE CONTROL
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