參數(shù)資料
型號： C8051F015-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 132/171頁
文件大小： 0K
描述： BOARD PROTOTYPING W/C8051F015
標準包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute, and usually have a maximum system clock of 12MHz. By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. The CIP-51 has a total
of 109 instructions. The number of instructions versus the system clock cycles required to execute them is as
follows:
Instructions
26
50
5
14
7
3
1
2
1
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the Flash program memory and
communication with on-chip debug support circuitry. The reprogrammable Flash can also be read and changed a
single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows
program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support circuitry facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints and watch points, starting, stopping and single stepping through program execution (including interrupt
service routines), examination of the program’s call stack, and reading/writing the contents of registers and memory.
This method of on-chip debugging is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers,
or other on-chip resources.
The CIP-51 is supported by development tools from Silicon Laboratories and third party vendors. Silicon Labs
provides an integrated development environment (IDE) including editor, macro assembler, debugger and
programmer. The IDE’s debugger and programmer interface to the CIP-51 via its JTAG interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also
available.
10.1.
INSTRUCTION SET
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51 instruction set.
Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the
binary and functional equivalent of their MCS-51 counterparts, including opcodes, addressing modes and effect
on PSW flags. However, instruction timing is different than that of the standard 8051.
10.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle
timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as
there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete
when the branch is not taken as opposed to when the branch is taken. Table 10.1 is the CIP-51 Instruction Set
Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
10.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory. In the CIP-51, the MOVX instruction can
access the on-chip program memory space implemented as reprogrammable Flash memory using the control bits in
the PSCTL register (see Figure 11.1). This feature provides a mechanism for the CIP-51 to update program code
and use the program memory space for non-volatile data storage. For the products with RAM mapped into external
data memory space (C8051F005/06/07/15/16/17), MOVX is still used to read/write this memory with the PSCTL
63
Rev. 1.7
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